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CP 208 Digital Electronics Class Lecture 6 March 4, 2009

CP 208 Digital Electronics Class Lecture 6 March 4, 2009. MOS Field-Effect Transistors (MOSFETs). 2. In This Class. We Will Discuss Following Topics : Chap 4 MOS Field-Effect Transistors 4.1 Device Structure and Physical Operation 4.2 Current-Voltage Characteristics

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CP 208 Digital Electronics Class Lecture 6 March 4, 2009

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  1. CP 208Digital ElectronicsClass Lecture 6March 4, 2009

  2. MOS Field-Effect Transistors (MOSFETs) 2

  3. In This Class We Will Discuss Following Topics: Chap 4 MOS Field-Effect Transistors 4.1 Device Structure and Physical Operation 4.2 Current-Voltage Characteristics 4.3 MOSFET Circuits at DC

  4. Introduction • Three Terminal Device – (as seen in BJT) the Control Signal used on Two terminals can cause Current to Change on Third from Zero to Hi value (switch) – Similar concept for MOSFET • Switch is Basis for Logic Inverter – basic Element of Digital Ckts/Electronics • MOSFET can be made Smaller than BJT, and Manf. Process is simple and Require Lower P • > 200 Mil MOSFETs on Single Chip • Can be used as Amp and Dig Logic Inverter

  5. 4.1.1 Physical STRUCTURE of Enhancement-type NMOS transistor: (a) perspective view; (b) cross-section. Typically L = 0.1 to 3 mm, W = 0.2 to 100 mm, and thickness of the oxide layer (tox) = 2 to 50 nm.

  6. 4.1.2 No Gate Voltage Operation • Two Back-to-Back Diodes in Series Between Drain and Source • Prevent Current Flow between Drain and Source when vDSis Applied • The path between Drain and Source has very High Resistance in the Order of 1012Ω

  7. 4.1.3 Creating a Channel for Current FlowPositive Voltage to gate Repels (Pushes) Holes Down in Substrate and Attracts Electron. When sufficient number of electrons gather under Gate an n-region is created thereby an n channel is INDUCED under the gate. Now if vDS is applied current will flow in n-region (n-Channel)

  8. Note … • Because of n-channel This MOSFET is called NMOS Transistor • n-Channel (or Inversion Layer) created by inverting the p-type sub to n-type with application of Gate Voltage (Field) • The value of vGS at which conducting channel is formed is called Vt(Positive for n) • Vt is controlled during fabrication process and typically range from 0.5 to 1 V • Gate and Channel form parallel plate capacitor (oxide as dielectric) creating the E filed in Vertical direction • E field controls the Charge in Channel and thus determines the conductivity of channel

  9. 4.1.4 Applying a Small vDS When a Small vDSis Applied along with vGS > Vt NMOS acts as a resistor whose value is determined by vGS Specifically, the channel conductance is proportional to Excess Gate Voltage (vGS – Vt), and thus iD is proportional to (vGS – Vt) vDS. (Depletion region not shown)

  10. The iD–vDS characteristics of the MOSFET When voltage applied between drain and source, vDS, is kept small, device operates as a linear resistor whose value is controlled by vGS. The increase of vGS above Vt Enhances the Channel, Hence Enhancement-mode or Enhancement-type MOSFET

  11. 4.1.5 Operation as vDS is increased.vGS is kept constant at a value > VtvDSappears as voltage drop across the channel L (voltage increases from 0 to vDS from S to D).Thus voltage between gate and points along channel decreases from vGS to vGS – vDS. Thus induced channel acquires a tapered shape, and its resistance increases as vDS is increased. And iD - vDS curve no longer straight line but bends – Next Figure

  12. When vDS increases to value so that voltage between gate and drain side of channel reaches Vt – vGD = Vt or vGS – vDS = Vt or vDS = vGS – Vt the channel depth at drain end is almost zero (or channel is pinched off) Increasing vDSbeyond this has no effect on channel shape and iD stays constant

  13. Eventually, as vDS reaches vGS – Vt’ the channel is pinched off at the drain end. Increasing vDS above vGS – Vt has no effect on the channel’s shape and current saturates and MOSFET has entered Saturation Region. That is, vDSsat = vGS– Vt Note That … For every value of vGS > Vtthere is corresponding vDSsat. Device in Saturation if vDS≥ vDSsat

  14. 4.1.6 Derivation of the iD–vDS Relationship

  15. 4.1.7 p-Channel MOSFET (PMOS) Fabricated on n-type substrate with p+ regions for D and S and p-channel is induced under gate Operates same way as n-channel device except vGS, Vt and vDS are negative Also, iD enters S and leaves D Because NMOS can be made smaller and operate faster and use lower supply voltage than PMOS, it has virtually replaced PMOS

  16. In Next Class We Will Continue to Discuss: Chap 4 MOS Field-Effect Transistors

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