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Platform Design Considerations

May 17, 2000. 3. Agenda. GuidelinesMeasurement TechniquesEarly Testing ResultsSummary. May 17, 2000. 4. Guidelines. USB 2.0 guidelines will be more systematic, detailed than 1.x whitepapersProposed guideline areas:Attenuation, jitter budgetsPackage/board/chassis designEMI/EMC Use of test m

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Platform Design Considerations

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    2. May 17, 2000 2 Platform Design Considerations Jim Choate Intel Corporation

    3. May 17, 2000 3 Agenda Guidelines Measurement Techniques Early Testing Results Summary

    4. May 17, 2000 4 Guidelines USB 2.0 guidelines will be more systematic, detailed than 1.x whitepapers Proposed guideline areas: Attenuation, jitter budgets Package/board/chassis design EMI/EMC Use of test modes and testing for compliance

    5. May 17, 2000 5 Board Design 4 layer sufficient; trace impedance matching is key 3 ns + 26 ns + 1 ns Avoid long runs Do not cross plane splits Minimize vias Maximize distance to other traces

    6. May 17, 2000 6 Board Design Guidelines Board Stack-up: 4 layer, impedance controlled boards required Impedance targets must be specified Ask your board vendor what they can achieve

    7. May 17, 2000 7 Routing Guidelines Control trace widths to obtain target impedance Ask your board vendor what they can achieve As always, cost is a consideration Maintain strict trace spacing control Minimize stubs

    8. May 17, 2000 8 Routing Guidelines Routing over plane splits Creating stubs with test points Violating trace spacing guidelines

    9. May 17, 2000 9 Measurement Techniques Selecting appropriate test equipment Accurate measurement of signal quality requires an oscope and probes with adequate BW and sample rate Proper test fixtures are also important

    10. May 17, 2000 10 Board Testing Use TDRs to verify adherence to budget Typical TDR measurement Refer to section 7.1.6.2 of the specification for details

    11. May 17, 2000 11 EMI USB1.X EMI solutions don’t work for USB2 Low pass filters damage signal quality

    12. May 17, 2000 12 EMI Proper grounding of chassis is crucial Connector shell must connect to green wire ground early and well IO shield must connect securely to chassis and receptacle 2 wire common mode choke is preferred Blocks common mode EMI from leaving chassis Differential signal rolloff frequency should be high

    13. May 17, 2000 13 ESD, EMC ESD strikes spread out in time by inductance of cables and hubs in series Bypass/flyback caps on Vbus near connector help Hardware Protection Well-grounded shield 4 wire common mode choke Spark gap arrestors Shielded cables

    14. May 17, 2000 14 ESD, EMC Differential squelch/disconnect Pattern matching before connectivity Sampling over extended times e.g. Chirp

    15. May 17, 2000 15

    16. May 17, 2000 16 Early Testing Results

    17. May 17, 2000 17 Early Testing Results Back panel eye pattern results EMI/ESD components Both at A-connector (TP2) and at end of USB cable (TP3) Three-stack connector on MB

    18. May 17, 2000 18 Board Design Daughtercard at front/side panel Bypass caps, EMI control components, strain relief Header and cable Keyed header, cable of limited length and matched impedance

    19. May 17, 2000 19 Early Testing Results Front Panel Header Cable Options Tested

    20. May 17, 2000 20 Early Testing Results Front-panel cable implementation eye pattern results 18 inch, twisted pair, shielded front panel cable 18 inch unshielded front panel “ribbon” cable

    21. May 17, 2000 21 Early Testing Results Front-panel cable implementation eye pattern results 18 inch, twisted pair, shielded front panel cable 18 inch unshielded front panel “ribbon” cable

    22. May 17, 2000 22 Summary USB 2.0 design presents new challenges Board layout Common mode chokes Chassis grounding Signal Quality Measurement Compliance Testing USBIF will be providing design guides in such areas

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