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TFET – a possible replacement for CMOS in low-power applications

TFET – a possible replacement for CMOS in low-power applications. Costin Anghel, Institut Superieur d'Electronique de Paris (Paris, FR). Outline : • Why do we need another new device? - Power Consumption Problem - CMOS vs. TFET • Tunnel FETs - Operation Principle

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TFET – a possible replacement for CMOS in low-power applications

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  1. TFET – a possible replacement for CMOS in low-power applications Costin Anghel, Institut Superieur d'Electronique de Paris (Paris, FR) C. ANGHEL

  2. Outline: •Why do we need another new device? - Power Consumption Problem - CMOS vs. TFET • Tunnel FETs - Operation Principle -State-of-the-art •Conclusion C. ANGHEL

  3. Outline: •Why do we need another new device? - Power Consumption Problem - CMOS vs. TFET • Tunnel FETs - Operation Principle -State-of-the-art •Conclusion C. ANGHEL

  4. Power Consumption Problem • Leakage power stars to be dominant in advanced technology nodes. • The power per chip continues to increase. E.J.Nowak, JRD IBM 2002 C. ANGHEL

  5. -3 10 -5 10 -7 10 -9 10 -11 10 0.0 0.3 0.6 0.9 Scaling limited by the 60mV/dec m) m Lower VT (A/ Vt • Scaling involves also the scaling of the threshold voltage (VT). DS • The subthreshold slope is limited to a minimum of 60mV/dec for CMOS Higher IOFF Drain Current, I “Lowering Vt by 60mV increases the leakage current (power) by 10 times.” C. HU – 2009 Gate Voltage, V (V) GS C. HU - 2009 C. ANGHEL

  6. Sources of Static Power - CMOS: C. ANGHEL Prof. A.M. IONESCU (EPFL) @ ESSDERC 2009

  7. Outline: •Why do we need another new device? - Power Consumption Problem - CMOS vs. TFET • Tunnel FETs - Operation Principle -State-of-the-art •Conclusion C. ANGHEL

  8. CMOS n-type TFET n-type Oxide Oxide Gate Gate Drain Drain Source Source n+ i n+ p+ i n+ TFET vs. CMOS CMOS: Pros.: classical device ION within the ITRS targets Cons.: power issue TFET: Pros.: Extremely Low IOFF SS below 60mV/dec Cons.: Low ION R&D needed C. ANGHEL

  9. Outline: •Why do we need another new device? - Power Consumption Problem - CMOS vs. TFET • Tunnel FETs - Operation Principle -State-of-the-art •Conclusion C. ANGHEL

  10. Cutline EC EV Energy [eV] Location [mm] TFET – the operation principle VG=0V VD=1V C. ANGHEL

  11. Energy [eV] Energy [eV] Location [mm] Location [mm] TFET – the operation principle TFET OFF state TFET ON state VG=0V VD=1V VG=1V VD=1V e- C. ANGHEL

  12. Outline: •Why do we need another new device? - Power Consumption Problem - CMOS vs. TFET • Tunnel FETs - Operation Principle -State-of-the-art •Conclusion C. ANGHEL

  13. TFET: State-of-the-art– CNTs J. Appenzeller et al., Phys.Rev. Lett. 93, (2004). C. ANGHEL

  14. TFET: State-of-the-art– Si Choi et al. Electr. Dev. Lett. 28, pp. 743 (2007). C. ANGHEL

  15. TFET: State-of-the-art– Si Second spacer used to create the gate- drain underlapping IOFF (~30fA/μm) ION (~10-7A/μm) F. Mayer et al, IEDM 2008. C. ANGHEL

  16. TFET: State-of-the-art– DG or GAA DG TFET with strained Ge heterostructure channel: ION high but IOFF and VD high T. Krishnamohan et al, IEDM 2008. C. ANGHEL

  17. TFET: State-of-the-art– DG or GAA IOFF (~7pA/μm) ION (~53mA/μm) ION/ IOFF=107 DIBL = 17mV/V Chen et al.,IEEE EDL, VOL. 30, p. 754, 2009. C. ANGHEL

  18. TFET: State-of-the-art– source delta doping R. Jhaveri, et. al. TED 01/2011, pp. 80. K. Jeon, et. al.VLSI, 2010. C. ANGHEL

  19. TFET: State-of-the-art– DG or GAA Source heterojunction increases the ION current IOFF current is mantained low. Anne S. Verhulst et al., IEEE EDL, Vol. 29, pp. 1398, 2008. C. ANGHEL

  20. TFET: State-of-the-art– DG or GAA Strained Si at the Source side – increase of ION current IOFF current is mantained low. Kathy Boucart et al., IEEE EDL, Vol. 30, p. 656, 2009 C. ANGHEL

  21. TFET: State-of-the-art– DG or GAA High k gate dielectrics - ION current in ITRS targets - IOFF current is mantained low. Difficult to integrate high k of 100 or 200 on Si platform… Schlosser et al. IEEE TED, vol. 56, p. 100, 2009. C. ANGHEL

  22. TFET: State-of-the-art– Spacer Influence High-k spacer The low-k spacer does not deplete the source Tunneling at the surface of the device @ highest field  Increased ION current Low-k spacer Anghel et al. APL, vol. 96, p.122104, 2010. C. ANGHEL

  23. TFET: Source Position and Film Thickness tSi=10nm Homo-dielectric structures: low ION variation as a function of source position Hetero-dielectric structures: important ION variation as a function of source position Hetero-dielectric structures: important ION variation as a function of tSi Anghel et al. accepted for publication IEEE TED, 2011. C. ANGHEL

  24. Conclusion: • TFET presents LOW IOFF and LOW ION and SS below 60mV/dec. • TFET can replace in the future the CMOS for low power applications Open Question: - ITRS LSTP roadmap was built on CMOS, should we rethink this roadmap from another perspective (i.e. the TFET one)? C. ANGHEL

  25. Many Thanks to: • Hraziia, Anju Gupta, Prathyusha Chilagani • Prof. Andrei Vladimirescu, Prof. Amara Amara Thank you for your attention! C. ANGHEL

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