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MonolithIC 3D ICs

MonolithIC 3D ICs. RCAT Flow. MonolithIC 3D Inc. , Patents Pending. Monolithic 3D ICs.

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MonolithIC 3D ICs

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  1. MonolithIC 3D ICs RCAT Flow MonolithIC 3D Inc. , Patents Pending MonolithIC 3D Inc. , Patents Pending

  2. Monolithic 3D ICs Using SmartCut technology - the ion cutting process that Soitec uses to make SOI wafers for AMD and IBM (million of wafers had utilized the process over the last 20 years) - to stack up consecutive layers of active silicon (bond first and then cut). Soitec’s Smart Cut Patented* Flow(access the link for video). *Soitec’s fundamental patent US 5,374,564 expired Sep. 15, 2012 MonolithIC 3D Inc. , Patents Pending

  3. Monolithic 3D ICs Ion cutting: the key idea is that if you implant a thin layer of H+ ions into a single crystal of silicon, the ions will weaken the bonds between the neighboring silicon atoms, creating a fracture plane (Figure 3). Judicious force will then precisely break the wafer at the plane of the H+ implant, allowing you to in effect peel off very thin layer. This technique is currently being used to produce the most advanced transistors (Fully Depleted SOI, UTBB transistors – Ultra Thin Body and BOX), forming monocrystalline silicon layers that are less than 10nm thick. MonolithIC 3D Inc. , Patents Pending

  4. Figure 3Using ion-cutting to place a thin layer of monocrystalline silicon above a processed (transistors and metallization) base wafer Cleave using <400oC anneal or sideways mechanical force. CMP. Hydrogen implant of top layer Flip top layer and bond to bottom layer Oxide p- Si Top layer Oxide p- Si H p- Si H p- Si Oxide Oxide Oxide Oxide Oxide Bottom layer Similar process (bulk-to-bulk) used for manufacturing all SOI wafers today MonolithIC 3D Inc. , Patents Pending

  5. MonolithIC 3D – The RCAT path • The Recessed Channel Array Transistor (RCAT) fits very nicely into the hot-cold process flow partition • RCAT is the transistor used in commercial DRAM as its 3D channel overcomes the short channel effect • Used in DRAM production @ 90nm, 60nm, 50nm nodes • Higher capacitance, but less leakage, same drive current The following slides present the flow to process an RCAT without exceeding the 400ºC temperature limit MonolithIC 3D Inc. , Patents Pending

  6. RCAT – a monolithic process flow Using a new wafer, construct dopant regions in top ~100nm and activate at ~1000º C Oxide P- ~100nm N+ P- Wafer, ~700µm MonolithIC 3D Inc. , Patents Pending 6

  7. Implant Hydrogen for Ion-Cut H+ Oxide P- ~100nm N+ P- Wafer, ~700µm MonolithIC 3D Inc. Patents Pending

  8. H+ Hydrogen cleave plane for Ion-Cut formed in donor wafer Oxide P- ~100nm N+ ~10nm P- Wafer, ~700µm MonolithIC 3D Inc. Patents Pending

  9. H+ Flip over and bond the donor wafer to the base (acceptor) wafer Donor Wafer, ~700µm N+ ~100nm P- Oxide 1µ Top Portion of Base Wafer Base Wafer, ~700µm MonolithIC 3D Inc. Patents Pending

  10. Perform Ion-Cut Cleave N+ ~100nm P- Oxide 1µ Top Portion of Base Wafer MonolithIC 3D Inc. Patents Pending Base Wafer ~700µm 10

  11. Complete Ion-Cut N+ ~100nm P- Oxide 1µ Top Portion of Base Wafer MonolithIC 3D Inc. Patents Pending Base Wafer ~700µm 11

  12. Etch Isolation regions as the first step to define RCAT transistors N+ ~100nm P- Oxide 1µ Top Portion of Base Wafer MonolithIC 3D Inc. Patents Pending Base Wafer ~700µm 12

  13. Fill isolation regions (STI-Shallow Trench Isolation) with Oxide, and CMP N+ ~100nm P- Oxide 1µ Top Portion of Base Wafer MonolithIC 3D Inc. Patents Pending Base Wafer ~700µm 13

  14. Etch RCAT Gate Regions Gate region N+ ~100nm P- Oxide 1µ Top Portion of Base Wafer MonolithIC 3D Inc. Patents Pending Base Wafer ~700µm 14

  15. Form Gate Oxide N+ ~100nm P- Oxide 1µ Top Portion of Base Wafer MonolithIC 3D Inc. Patents Pending Base Wafer ~700µm 15

  16. Form Gate Electrode N+ ~100nm P- Oxide 1µ Top Portion of Base Wafer MonolithIC 3D Inc. Patents Pending Base Wafer ~700µm 16

  17. Add Dielectric and CMP N+ ~100nm P- Oxide 1µ Top Portion of Base Wafer MonolithIC 3D Inc. Patents Pending Base Wafer ~700µm 17

  18. Etch Thru-Layer-Via and RCAT Transistor Contacts N+ ~100nm P- Oxide 1µ Top Portion of Base Wafer MonolithIC 3D Inc. Patents Pending Base Wafer ~700µm 18

  19. Fill in Copper N+ ~100nm P- Oxide 1µ Top Portion of Base Wafer MonolithIC 3D Inc. Patents Pending Base Wafer ~700µm 19

  20. Add more layers monolithically N+ ~100nm P- Oxide N+ ~100nm P- Oxide 1µ Top Portion of Base (acceptor) Wafer Base Wafer ~700µm 20 MonolithIC 3D Inc. Patents Pending

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