1 / 27

ECE 4110/5110: Digital System Design

ECE 4110/5110: Digital System Design. ECE 4110– Digital System Design. Lecture #1 Agenda Course Logistics Course Content Digital Review Announcements Welcome Homework #1 assigned. Course Overview. Instructor: Omar Elkeelany

lorene
Download Presentation

ECE 4110/5110: Digital System Design

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript


  1. ECE 4110/5110: Digital System Design ECE 4110– Digital SystemDesign

  2. ECE 4110– Digital System Design Lecture #1 • Agenda • Course Logistics • Course Content • Digital Review • Announcements • Welcome • Homework #1 assigned

  3. Course Overview • Instructor:Omar Elkeelany • Office : 332 Brown Hall Phone : (931)-372-3450 Email : oelkeelany@tntech.edu Web : http://iweb.tntehc.edu/oelkeelany

  4. Course Overview • Textbook:“Digital Design: Principles and Practices", 4th Addition John F. Wakerly, Prentice Hall, 2006 • Website:http://iweb.tntech.edu/oelkeelany/4110F13 • all handouts, homework assignments are ONLINE • it is your responsibility to download assignments

  5. Course Overview • Pre-requisites:ECE2110 / ECE3160 • Grading:Homework/VHDL and Quizzes 20% Combo System project 20% Exam #1 20% Exam #2 20% Final Exam 20% - Homework Assignments are due at the beginning of class. - No Late homework will be accepted. - No make up exams will be given, unless pre-excuesd before the test. Plan on being available on the exam dates. - Term paper assignment will be given for 5110 graduate level.

  6. Course Overview • Where does this course fit into the Electrical Engineering curriculum?

  7. Course Overview • Where does this course fit into the Computer Engineering curriculum?

  8. Course Content • What is this course?- In ECE2110 you learned: - basic combinational logic design - basic sequential logic design- In ECE3160 you learned: - how to implement logic circuits using off-the-shelf parts- ECE4110 is a follow-on course that looks at: - Large scale digital designs - Performance of digital circuitry - Programmable Logic

  9. Course Content • What does "Large" mean? - Large means that you can't do it by hand. We need a way to design and simulate Millions of gates- K-maps for a Pentium would take too much paper

  10. Course Content • We will learn VHDL in order to describe large digital designs - VHDL is a text based Hardware Description Language - We can simulate our digital designs created in VHDL

  11. Course Content • We can also prototype our designs using an FPGA - FPGA = Field Programmable Gate Array - An FPGA is a programmable logic device - In this course, • we will implement our designs and test them in FPGA hardware

  12. Course Content • What topics will be covered?1) VHDL (Exam #1 Topics) 2) Medium Scale Combinational Logic Devices 3) More Complex Finite State Machines (Exam #2 Topics) 4) Computer Systems5) FPGA Timing and Implementation • For the 5110 level, a special assignment is to: Write an original research paper on a topic related to those in this course, such as: • Modern programmable logic devices, survey, features, comparisons, usage, etc.. • Hardware description languages: survey, comparisons, usage, IP, etc. • Sequential Logic Design methods

  13. Digital Review Combinational Logic Combinational Logic Gates : - Output depends on the logic value of the inputs - no storage

  14. Digital Review NOT out = in’ = in f(in) = in’ = in OR out = a+b f(a,b) = a+b AND out = a·b f(a,b) = a·b

  15. Digital Review XOR out = ab f(a,b) = ab NOR out = a+b f(a,b) = a+b NAND out = a·b f(a,b) = a·b

  16. Digital Review XNOR out = ab f(a,b) = ab Also remember about XOR Gates: f(a,b) = ab = (a’b + b’a) Also remember the priority of logic operations (without parenthesis) is: NOT, AND, OR

  17. Digital Review DeMorgan’s Theorems • Inverting the output of any gate results in the same function as the opposite gate (AND/OR) with inverted inputs

  18. Digital Review DeMorgan’s Theorems • Graphically : breaking the bar changes the logic function (AND-OR) under the break out = a+b 1) Break bar out = a+b 2) Change + to · under break out = a·b

  19. Digital Review Boolean Expressions Using SOP • Logic functions can be described using a Sum of Products techniques • Sum of Products (SOP) is the summation of all minterms resulting in the truth table • A minterm is the expression for an input configuration which yields a TRUE output • A minterm expression is the AND’ing of the input "1" signal configuration Truth Table about 0 0 0 0 1 1 minterm m1 = a’·b 1 0 1 minterm m2 = a·b’ 1 1 0 SOP Expression : f(a,b) = a’·b + a·b’ Note : un-minimized Boolean expression

  20. Digital Review Boolean Expressions Using POS • Logic functions can be described using a Product of Sums techniques • Product of Sums (POS) is the multiplication of all maxterms resulting in the truth table • A maxterm is the expression for an input configuration which yields a FALSE output • A maxterm expression is the OR’ing of the input "0" signal configuration Truth Table about 0 0 0 maxterm m0 = a+b (input configuration of 0's) 0 1 1 1 0 1 1 1 0 maxterm m3 = a'+b' (input configuration of 0's) POS Expression : f(a,b) = (a+b) · (a'+b')

  21. Digital Review Boolean Expressions Using SOP & POS • SOP and POS functions are equivalent SOP Expression : f(a,b) = a’·b + a·b’ is equal to POS Expression : f(a,b) = (a+b) · (a'+b')

  22. a 0 1 b 0 1 0 1 1 1 Digital Review Karnaugh Maps • K-maps provide a graphical method to find SOP/POS expressions • K-maps also provide a graphical method to perform logic minimization K-map SOP Process 1) Circle minterms to create SOP 2) Circle in Horizontal & Vertical manner 3) Circle in groups with powers of 2 (1,2,4,8,…) Truth Table about 0 0 0 0 1 1 1 0 1 1 1 1 No dependency on b, minterm = a No dependency on a, minterm = b SOP expression : f(a,b) = a + b

  23. a 0 1 b 0 1 0 1 1 1 Digital Review Karnaugh Maps • K-maps provide a graphical method to find SOP/POS expressions • K-maps also provide a graphical method to perform logic minimization K-map POS Process 1) Circle maxterms to create SOP 2) Circle in Horizontal & Vertical manner 3) Circle in groups with powers of 2 (1,2,4,8,…) Truth Table about 0 0 0 0 1 1 1 0 1 1 1 1 Dependency on a' and b', maxterm = a+b POS expression : f(a,b) = a + b

  24. D Q Q Q Digital Review Sequential Logic - Concept of “Storage Element” - With Storage, logic functions can depend on current & past values of inputs - Sequential State Machines can be created D-Flip-Flop - on timing event (i.e., edge of clock input), D input goes to Q output CLK D Q tc2q

  25. Digital Review State Machines - Moore : Outputs depend on present state - Mealy : Outputs depend on present state and current inputs

  26. 00 01 11 10 Digital Review State Machine Example : Design a 2-bit Gray Code Counter 1) Number of States? : 4 2) Number of bits to encode states? : 2n=4, n=2 3) Moore or Mealy? : Moore For this counter, we can make the outputs be the state codes

  27. 00 01 11 10 D D Q Q Q Q Digital Review State Machine Example : Design a 2-bit Gray Code Counter STATE CurrentNext Acur Bcur Anxt Bnxt 0 0 0 1 0 1 1 1 1 1 1 0 1 0 0 0 Anxt Logic Bnxt Logic Bcur0 1 Bcur0 1 Acur 0 1 Acur 0 1 0 1 1 1 0 1 0 0 Bnxt = Acur’ Anxt = Bcur A counter output B A B CLK

More Related