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EE 501 Fall 2009 Design Project 1

EE 501 Fall 2009 Design Project 1. Fully differential multi-stage CMOS Op Amp w ith Common Mode Feedback a nd Compensation for high GB. Major components. Input differential pair Cascoding for boosting DM gain, CMRR Second gain stage Compensation Common mode feedback

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EE 501 Fall 2009 Design Project 1

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  1. EE 501 Fall 2009Design Project 1 Fully differential multi-stage CMOS Op Amp with Common Mode Feedback and Compensation for high GB

  2. Major components • Input differential pair • Cascoding for boosting DM gain, CMRR • Second gain stage • Compensation • Common mode feedback • Biasing circuits • VDD independent current reference (T independence not required for this project but is for next project) • Start up circuit

  3. Input differential pair • NMOS input vs PMOS input • Transconductance gain gm requirement • Noise consideration • Area, mismatch, and offset voltage issues • Common mode rejection • Tail current source: cascode or not • Effects on CMRR, ICMR • Input common mode range • Choice of telecopicvs folded cascode • Choice of VEB’s and Vbias for cascode

  4. What are the advantages/disadvantages of cascoding M5? Which one offers better differential signal virtual ground at S1/S2? Which one offers better Vicm-min? Which one offers better Vicm rejection? Which one offers better power supply rejection? Which one is more area efficient?

  5. What are the advantages/disadvantages of NMOS input vs PMOS input? Which one offers better differential signal transconductance? Which one offers better 1st stage – 2nd stage current split considerations? Which one offers better 1/f noise contribution? Which one offers better input referred thermal noise? Which one offers better off set voltage?

  6. Cascoding • Telescopic cascode • Folded cascode

  7. Telescopic N-input

  8. Telescopic P-input

  9. Folded cascode P-input

  10. Second gain stage • NMOS input • PMOS input • Current source load • Cascode load

  11. Compensation • Miller compensation • Rz-Cc compensation • Implementation • Process tracking bias • Cc feeding back to cascode • Cc feeding back to triode node

  12. Common mode feedback

  13. Biasing circuit

  14. VDD independent reference

  15. Startup circuit

  16. First stage bias constraints: Vbb = Vdd – |Vtp| – Veb3 Vxx < Vdd – Vsdsat3 – |Vtp| – Veb3c Vyy < Vdd – Vsdsat3 – Vsdsat3c + Vtn1c Vicm > Vicmmin = Vss + Vdssat7 + Vtn1 + Veb1 Vicm < Vicmmax= Vyy– Vdssat1c Vicmr = Vicmmax – Vicmmin <Vdd – Vss – Vsdsat3 – Vsdsat3c – Vdssat7 – Vdssat1c + Vtn1c – Vtn1 – Veb1 This must > specification

  17. Second stage bias constraints: Vo+ < Vdd – Vsdsat6 Vo+ > Vss + Vdssat7 Vzzdoes not have to be the same as that in first stage Vo1- is not fixed, Vsdsat5 is varying with signal. Vo1 needs to be able to swing high enough to turn off M6, so Vo1max >= Vdd– |Vtp| Vo1 needs to be able to swing low enough for M6 to provide 2*I7=2*I6Q for charging CL, so Vo1min <= Vdd – |Vtp| – sqrt(2)Veb6Q Vo1DSW = Vo1max – Vo1min >= sqrt(2)Veb6Q This Vo1 swing range should be subtracted from the max V_ICMR

  18. So worst case Vsdsat6: sqrt(2)*Vsdsat6Q Vo+ should be clear of this. If Vo range is symmetric, this gives enough room to put a cascode on M7 to reduce ro and Co. Inter-stage bias constraints: Vo1 range must accommodate Vg6 needs, and Vg6 ranges from Vdd – |Vtp| to Vdd – Vtp| – sqrt(2)*Veb6Q Therefore we need: Vsdsat3+Vsdsat3c < |Vtp| so that when Vg6 = Vdd–|Vtp| M3 and M3c are still in saturation. We also need: Vyy < Vdd – |Vtp| – sqrt(2)*Veb6Q + Vtn1c so that when Vg6 is the lowest M1c is still in saturation. Vicmmax = Vyy – Vdssat1c < Vdd – |Vtp| – sqrt(2)*Veb6Q – Vdssat1c + Vtn1c Vicmr <Vdd – Vss – |Vtp| – sqrt(2)*Veb6Q – Vdssat7 – Vdssat1c + Vtn1c – Vtn1 – Veb1

  19. Slew rate constraints To charge and discharge CL and Cc, current goes from Vo node into or out of these caps. Cc dVo/dt + CL dVo/dt = I6–I7 max|dVo/dt| <= I7/(CL+Cc) The other end of Cc goes to Vo1 node. Cc dVo/dt + I3 = I1 max |dVo/dt| <= I1Q / Cc If SR is limiting factor, we don’t want to waste any current, and we should have SR = I6Q/(CL+Cc) = I1Q / Cc I6Q : I1Q = (CL+Cc) : Cc This significantly limits freedom in Cc and current split choices.

  20. If SR is not the performance limiter, can have the Cc charge discharge slower than CL. In this case: SR = I1/Cc If we have put most of the current into 2nd stage, and chosen Cc to be large compared to CL (CL/Cc ratio small), SR can be small. This leads to constant slope slewing in large size step response and in large magnitude sinusoidal output at near GB frequencies. This in turn leads to increased nonlinearity at high frequencies and high signal magnitudes.

  21. Design steps for max GB • From total power allowance, compute Itot Itot = Ptot/(VDD-VSS) • Assume that about 5 to 10 % of the current budget will go to reference and biasing circuits, 90 to 95% is available for 1st and 2nd stages. As a starting point, take I6 = ¾ Itot • Sizing of M6 • For high speed, take small L6, e.g. L6 = L_min or 1.5L_min • For maximum GB, we maximize |p2| W6 = CL/(2C_j L_drain + C_oxL6) • Compute: Cdb6 = CjL_drainW6 + 2C_jsw(L_drain+W6) Cgs6 = C_oxW6 L6 gm6 = sqrt(2 I6 uC_oxW6/L6) |p2| = gm6 / (CL + Cgs6 + 2Cdb6) ≈gm6 / 2CL

  22. Design steps for max GB • Select Cc: Cc <= min{0.5 CL, 0.4 I_tot / SR} e.g. take Cc = 0.2 CL • Compute gm1 and I5 I5/2 >= SR * Cc, and watch I5 + I6 to be about 0.9 I_tot if I5 too large, reduce Cc Let GB = |p2|, gm1/Cc = gm6/2CL gm1 = gm6 * Cc/2CL,  0.1gm6 • Size M1/M2: Take L1 to be 1.5 or 2 L_min W1 = gm1^2 L1 /{uC_ox I7} If 1/f is concern, increase L1 and W1 together. • In the cascoded case, Vds3 and Vds4 are matched. Size (W/L)3 so that Veb3 to be about 1/3 |VTP|

  23. Design steps for max GB • M7, M5 and M0 all share the same Vgs that comes from the biasing circuit Select a suitable VEB of about 0.3 V for them Select the same L for all three W5 = 2 I5/ VEB^2 / uC_ox W7 = 2 I7/ VEB^2 / uC_ox Take W0 to be about 5% W6 so that its current is about 5% • Sizing M8, M9, Rz Let M8 have the same L as M5 W8 to W5 ratio to be the same as W0 to W6 ratio Let M9 have the same W/L as M8, Rz have the same L Perform parametric scan of W for Rz, to achieve best PM

  24. VDD VDD VDD M6 M2 M7 M1 M5 CC CL Vyy M4 M3 M4c M3c vo M1c M2c Vin+ Vin-

  25. Design steps for max GB • You can size M3c and M4c to be about the same as M3 and M4 Vdssat3c,4c are also about Veb3 Vdd-Vd3c is about 3 or 4 time Veb3 This makes it easy to ensure both M3 and M3c to be in saturation • Size the resistor and watch how Vd3 changes Choose the resistor value so that Vd3 is right in the middle of Vdd and Vd3c This gives Vds3 = Vds3c = ½ Vgs3 = ½ (1 + 1/3)VTP = 2/3 VTP Both M3 and M3c are in saturation Since Vds4 = Vds3, M4 is in saturation Vds4c = Vgs5 – Vds4 = Vtp+Veb5 -2/3Vtp =1/3Vtp +Veb5 As long as Veb5 > 0, M4c is in saturation

  26. VDD VDD VDD M6 M5 M7 CC CL M4 M3 3B M4c M3c 4B vo 5B M1c M2c 1B 2B Vin- Vin+

  27. Design steps for max GB • Size M1c and M2c to be about the same as M1,2 • Size M1B and M2B to have W/L ratio that is about 5 to 10% of M1 Total current in M1B M2B is about 5 to 10% of I7 Vdd-Vd3c is about 3 or 4 time Veb3 This makes it easy to ensure both M3 and M3c to be in saturation • Match M3B and M4B Their sizes are non-critical But use reasonable Veb • Size M5B to create the correct bias for M1c,2c Choose its W/L ratio so that Veb5b is 3 to 4 times Veb1 This guarantees saturation of M1,2 and M1c,2c

  28. Bias generator

  29. Design steps for max GB • For simplicity, you can have all M1 through M4 in the bias circuit to be the same size • M6 is the tail current source in first stage • M5 is not needed in the self biasing design • Let W/L ratio of M1-4 to be about 1/10 of (W/L)_tail • This creates a current of about 1/10 I7 • M4 and M5 has better match than M6 and M1 • You could flip up down for better matching • Size resistor • Scan resistor value to achieve I1, I2 that you want • Size shaded part so that • Current in M8 is tiny • Vg8 =Vg7 > 3Vtn but < 3Vtn + Veb1 + Veb2

  30. VDD VDD VDD M6 M2 M1 M7 M5 CC CL Vyy M4 M3 M4c M3c vo M1c M2c Can feed to here also Vin+ Vin-

  31. The Miller capacitor Cc sees an amplifier consisting of a common gate amplifier M4c followed by a common source amplifier M6. This amplifier’s low frequency gain is The miller capacitance seen at D4 is very large: The impedance at this node is: 1/gm4c This node gives the lowest frequency pole which determines the bandwidth of the amplifier:

  32. The DC gain of the amplifier is The gain bandwidth product is then The max rate of Vcc can change is when all of first stage current goes to charge CC. Hence, slew rate is

  33. VDD VDD M6 M2 M7 CC CL To calculate zero: Set Vo = 0 and all DC voltage to gnd M4 Vd4 = Vcc Vg6= Vcc*gm4c/g01 M4c vo Icc + gm6 Vg6=0 M2c sCc + gm6gm4c/g01=0 Z1= – gm6gm4c/(g01Cc) Vin- At extremely high frequency! Cannot be used to cancel a pole near unity gain frequency!

  34. VDD VDD M6 M2 M7 CC CL Alternative compensation for removing right-half plane zero: M4 M4c vo Noncascode version: M2c Vin-

  35. Need to add start-up circuit • Add MOSCAPs between VBP and VDD, and between VBN and VSS • NMOS W ratio and R determines current value • Cascode to improve supply sensitivity • Or use a regulate amp • VBN and VBP may be directly used as biasing voltage for non-critical use

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