Sonics Bus Modeling for Felix/VCC

Sonics Bus Modeling for Felix/VCC EE249 Project Presentation December 3, 1999 Mike Sheets

Introduction • What is involved in a bus model? • Sonics two level arbitration scheme • Modeling the arbiter in VCC • Performance simulation • Problems with the model Modeling Sonics in Felix/VCC

Modeling in Felix/VCC • Architecture exploration requires mapping behavior onto architecture • SiliconBackplane is fundamentally a bus • Bus models are fundamentally arbitration models • Can model Sonics architecture by adding a new arbiter to VCC Modeling Sonics in Felix/VCC

TDMA Arbitration • Time Division Multiple Access • Each slot is allocated to at most one transmitter • Each slot has a fixed time duration • Each frame contains n slots • Frame repeats continuously slot (time slice) 0 1 2 3 4 5 … n-1 0 1 2 3 … frame (length n) Modeling Sonics in Felix/VCC

Token Passing Arbitration 0 • Token Passing Arbitration (Round Robin) • Token is passed in a predefined order • Transmitter can only send when has token • When finished transmitting, passes token on n-1 1 current token owner … 2 3 Modeling Sonics in Felix/VCC

Fixed slots Guaranteed bandwidth Potentially wasteful Tokens Guaranteed fair, but might slow down fast initiators Slot allocated when needed Bus Arbitration Scheme Reliability TDMA Round-robin (token passing) Flexibility Modeling Sonics in Felix/VCC

Sonics Hybrid Arbitration Scheme • Implemented as two tiers, slice (TDMA) and token (round robin) • Owner of the slice gets right of refusal • If owner not ready to send, uses token arbiter • Can trade-off between slice, token, and both to balance reliability and flexibility Modeling Sonics in Felix/VCC

Sonics Bus Model Arbiter • Flexible bandwidth arbitration model • TDMA slot map gives slot owner right of refusal • Unowned/unused slots fall to round-robin arbitration • SBClk typically different from IClk and TClk so synchronization required • Latency after slice granted is user-specified between 2-7 SBClk cycles IClk SBClk SBClk TClk Initiator Core Initiator Agent Interconnect Target Agent Target Core OCP OCP Processor Clock synch., SB handshaking Pipelined commands Posted writes Selectable read latency Clock synch., SB handshaking Memory, I/O ports Sender Sonics SiliconBackplane Receiver Modeling Sonics in Felix/VCC

Sonics Architecture • Cores conform to Open Core Protocol (OCP) • SiliconBackplane is synthesized by Sonics tools Modeling Sonics in Felix/VCC

Behavioral Model • Four initiator agents and four target agents in a daisy-chain • Initiator agent access patterns are uniform pulse trains • Target agents simply sink the data Modeling Sonics in Felix/VCC

Hardware Mapping • TestCores mapped to hardware cores • Communication mapped to SiliconBackplane Modeling Sonics in Felix/VCC

Arbitration Model in VCC Sender 1) Posted write 2) Submit transaction Arbiter CTA Behaviors run continuously 3) Complete transaction Receiver 4) Receive data instantaneous time delay Modeling Sonics in Felix/VCC

Communication Delay Model • Receive a bus transaction • Synchronize request to SiliconBackplane clock • Arbitrate multiple simultaneous requests to determine the correct time slice • Add SiliconBackplane pipeline delays • Notify communication complete Modeling Sonics in Felix/VCC

Sonics Arbiter Parameters • Bus parameters • TDMA time-wheel counter maximums • Token-passing order • Bus frequency • Initiator parameters (communication link) • Arbitration policy (slice, token, both) • TDMA look-up table (slot map) • Minimum number of slots between requests Modeling Sonics in Felix/VCC

Simulation Results • Gantt charts show access pattern Legend Modeling Sonics in Felix/VCC

Simulation Results (2) • Statistics are provided in tabular form • Bus utilization (total or per initiator) • Arbitration mean latency (total or per initiator) • Most/least utilized connection • Results used to tweak arbitration parameters • Arbitration policy, slot map, token ordering • Bus frequency Modeling Sonics in Felix/VCC

Queuing Receiver Communication • Can be implemented using behavior framework • Code generation for queue • Estimation for queue Sender Posted write Arbiter CTA Data available Receiver Queue Acknowledge Posted writes can come at any rate handshake Modeling Sonics in Felix/VCC

Queuing Sender Communication Need a handshake here, but the required signals are not available • Output queue behavior cannot be implemented using any current VCC framework • Can fake it by adding CTA queues inside arbiter • Problem is being addressed in a future version of VCC Sender Queue Arbiter CTA Receiver Posted writes can come at any rate Modeling Sonics in Felix/VCC

Summary • Sonics SiliconBackplane can be implemented as an arbiter model in VCC • Mapping communication to the arbiter model yields useful bus utilization statistics • Model is cycle accurate, but made fast by skipping unimportant cycles • Queuing model in VCC has some problems Modeling Sonics in Felix/VCC

Sonics Bus Modeling for Felix/VCC