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Summary of EOC demonstrator submission

Summary of EOC demonstrator submission. presented by A. Kluge CERN/PH-ESE March 31, 2009.

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Summary of EOC demonstrator submission

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  1. Summary of EOC demonstrator submission presented by A. Kluge CERN/PH-ESE March 31, 2009 A. Klugea, G. Dellacasab, M. Fiorinia, P. Jarrona, J. Kaplona, F. Marchettob, E. Martina,d, S. Martoiub, G. Mazzab, M. Noya, A. Cotta Ramusinoc, P. Riedlera, A. Rivettib, S. Tiuraniemia a CERN, Geneva Switzerland, bINFN Torino, Italy, cINFN Ferrara, Italy, dUCL Louvain la Neuve, Belgium

  2. Outline • General architecture • submission procedure • submission problems A. Kluge

  3. EOC column architecture A. Kluge

  4. Jitter-free pixel signal to TDC in EOC amplifier & discriminator/time-walk-compensator reference clock time-to-digital converter TDC buffering & read-out processor A. Kluge

  5. 45 45 45 45 45 40 Hit Arbiter Hit Arbiter Hit Arbiter Hit Arbiter Addr. Addr. Addr. Addr. 32 Hit Reg2 Hit Reg1 Hit Reg2 Hit Reg1 Hit Reg2 Hit Reg1 Hit Reg2 Hit Reg1 LVDS Ref CLK 320MHz DLL Digital processing serializer 45 x 40 pixel final chip

  6. 45 x 1 demonstrator 45 45 Hit Arbiter Addr. 32 Hit Reg2 Hit Reg1 LVDS Ref CLK 320MHz DLL Digital processing serializer

  7. 45 x 1 demonstrator 45 EOC0 Hit Arbiter Addr Pileup 32 Hit Reg2 Hit Reg1 EOC1 EOC2 EOC3 EOC4 EOC5 EOC6 EOC7 EOC8 Ref CLK 320MHz serializer & LVDS DLL

  8. Pixel cell frontend A. Kluge

  9. Pixel cell frontend A. Kluge

  10. Pixel cell frontend • Preamp; buffered cascode (NMOS input transistor), resistive feedback (200k) • Gain;70mV/fC (25mV/fC at preamp output) • Preamplifier AC coupled to shaper and discriminator stages • Consumption; 190 µA/pixel (70 µA in analog section, 40 µA digital part of comparator, 80 µA line driver ) A. Kluge

  11. 5 32 to 5 bit encoder hit rising Hit Register 1 t0,t1,t3,…,tN-2,tN-1 DLL Ref CLK hit trailing Hit Register 2 5 32 to 5 bit encoder Time to Digital Converter • Tapped delay line • 32 cells, 100ps • Two hit registers • One per both leading and trailing edge • 5 bit encoding

  12. Optimisation of transmission line drivers – pre-emphasis

  13. Optimisation of transmission line drivers Amplitude Pre-emphasis

  14. Transmission of pixel hit A. Kluge

  15. Transmission of pixel hit A. Kluge

  16. hit Arbiter • Aynchronous latch logic which • defines first arriving pixel hit out of 5 in one group • latches hit address unambiguiously • during time-over-threshold time + TDC acquisition time: ~ 10 ns, address of additional (piled up) hits in same pixel group is stored A. Kluge

  17. Read-out • mode pin selects between 45 pixel column or 7 pixel column • 9 x 320 MHz data stream • can be disabled individually to test dependency on digital noise • read-out is continuous stream of data • Verilog description of ASIC block & deserializer available A. Kluge

  18. Several design changes after October-design-review on system level and on building block level. • 4 design areas: • Analog front-end – pixel cell • hit information driver/receiver – pixel cell & EOC • TDC & DLL & hit Arbiter – EOC • digital read-out block – EOC • Design changes were practically terminated 3 weeks before submission dated A. Kluge

  19. 4 design areas: • Analog front-end – pixel cell • hit information driver/receiver – pixel cell & EOC • TDC & DLL & hit Arbitrer – EOC • digital read-out block – EOC A. Kluge

  20. Layout –EOC 130µm 2.8 mm 6.7 mm A. Kluge

  21. Layout –EOC 130µm test pads Receiver 2x23 test pixels 1 folded column of 45 pixels Analogue test structures EOC Data grouping & pixel address 2.8 mm test pads pads test pixels Receiver 2x23 6.7 mm A. Kluge

  22. Layout –EOC 130µm test pads 1 folded column of 45 pixels Analogue test structures EOC Data grouping & pixel address 2.8 mm test pads pads sensor 4.14 x 5.37 mm2 6.7 mm A. Kluge

  23. 2 rows ASIC pads layout Sensor edge ASIC >300 µ 88 µ at least 900 µ 125 µ (90 µ?) 50 µ 125µ (90 µ?) 50 µ 62 µ 50 µ 2000

  24. Submission issues • Problems with submission of automatically generated digital blocks (in LM) in custom layout (in DM) • Problems with use of library I/O Pads both for design rule checks (ESD) and LVS (Calibre) • Elena (&Jan & Xavier) were working for 3! weeks • At the end (simpler) Angelo-custom made pads were used A. Kluge

  25. Submission • Chip has been submitted: • final LVS OK (with parameter mismatch due to extraction of gate around). • LVS has been checked also after stream in (with some problems in LVDS_TX due to hierarchy; solved by flattening of the transmitter cell). • The new pads gives many ESD errors both in assura and calibre; difficult to solve in short time (new pad library needed). • Antenna errors with assura not detected (clean), few antenna errors with caliber (related to input bump bonding pad and triple well (this error appears only when chip option is switched -> most probably bug in caliber deck)) A. Kluge

  26. Submission • LVS match on full chip • DRC check, waivers on ESD design rules • Layout optimisation is possible – long lines between building blocks • Further simulation allows optimisation of full custom TDC part with automatically generated parts A. Kluge

  27. Summary • Ambitious demonstrator functionality compared to initial approach • Difficult implementation as design kit needs optimisation and technology is new to us • These problems must be cleared for final submission • However, all LVS, DRC done • Required pre-submission simulations have been done A. Kluge

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