Outline

1. CALIBRATION OF TEVATRON IONIZATION PROFILE MONITOR (IPM) FRONT END (FE) MODULESMoronkeji BandelePhysics and Engineering DepartmentBenedict College, Columbia, South CarolinaSummer Internships in Science and TechnologySupervisor: Kwame Bowie

2. Outline • Motivation • Tevatron IPM DAQ System • Tevatron IPM Front End (FE) Board • Research Objectives • Experimental Analysis • Material Preparation • Initial Function Test • Charge Injection Calibration Test • Long – Term Stability Test • Data Analysis / Calculations • Gain Plots • Conclusions • Future Works • Acknowledgements Bandele

3. Motivation • A Data Acquisition (DAQ) instrument for Tevatron • Tevatron Ionization Profile Monitor (IPM) System - tomonitor the proton and antiproton beam bunch size and position at a fixed location in the Tevatron • IPM Front End (FE) Components: • In – Tunnel Subsystem • Upstairs Subsystem – implements all the intelligence and control for the Tevatron IPM DAQ system. The Tevatron and Main Injector rings Bandele

4. Motivation • In – tunnel Subsystem (Single Euro Card Crate) • Backplane – serves as medium for power supply • Fan – out card – duplicates signals it receives from timing card • Front – end (FE) boards – houses the very important QIE8 chip, developed by engineers at Fermi Lab. • Upstairs Subsystem (Single PC) • Timing Card – timing card sends signals to the Euro card crate (fan – out card) on a single CAT5 cable. • Buffer Boards – stores data received Buffer Card Fan – out Card Bandele

5. Tevatron IPM System flow chart Host PC (Labview) Data Buffer (2*8 ch) PCI Timing card (PCI) QIE cards (16x 8 ch) Timing fan-out Upstairs Subsystem In – tunnel Subsystem Bandele

6. Tevatron IPM DAQ System Trigger PC Pulse Generator Euro card Crate Power supply Oscilloscope Oscilloscope Backplane Fan-out card Optical Fiber CAT5 Cable Bias Resistor Timing/Clock signal FE Boards Schematic Diagram of Experimental Setup Pulse – carrying Cable Analog Pulse Channel selectors Computer screen Bandele

7. Materials Preparation • Solder bias resistor onto cable • Connect cable to channel selector • Insert board (s) into Euro card crate • Insert optical fiber into the optical data link • Connect CAT5 cable into PC and Euro card crate • Connect charge – carrying table to FE board • Power on the pulse generator, power supply, oscilloscope Bandele

8. Material Preparation Channel Selectors Resistors Oscilloscope Power Supply system FE Boards in Euro card crate Bias resistor soldered to cable Bandele

9. Tevatron IPM System Actual Experimental Setup Bandele

10. Tevatron IPM FE Board • Front End portion of the IPM DAQ system • Contains the very important radiation tolerant Application Specific Integrated Circuit (ASIC), QIE8, developed by engineers at Fermi Lab. QIE8 uses parallel circuitry to achieve a dead timeless continuous integration. • FE board functions • QIE8 Chip integrates and digitizes charge received at its input channels • Generate timing and error information for each beam bunch • Transmit data to Buffer Boards via optical link Bandele

11. Front End (FE) Card QIEs, Biasing, and Interface 9 Bits Power Supply Logic and Control FPGA Module 9 Bits 9 Bits Clock Distribution Circuitry QIE clock = 15 MHz Serializer clock = 40MHz 9 Bits 8 Point to point PECL Clock Pairs 9 Bits 9 Bits Header Word 9 Bits 9 Bits Serializer 1.6Gb/s Optical Link Laser Optical Module PECL QIE clock BACKPLANE Bandele

12. IPM FE CARD Overview 1 2 • Optical Link • Clock Distribution • Crystal Oscillator • CERN GOL • FPGA • Analog Connectors • QIE8 Chips • Glue Logic • Power Regulator • Backplane Connectors 3 7a 10a 8a 7b 6a 4 7c 8b 5 7d 7e 8c 9a 7f 10b 6b 7f 8d 9b 7g Bandele

13. Research Objectives • To test/calibrate the boards • To collect charge data • To analyze data • Testing Process • Initial Functional Test • Charge Injection Calibration Test : Research Focus • Long Term Stability Test Bandele

14. Initial Function Test • Insert FE boards into Euro card crate • Supply power through backplane • Run boards for five consecutive events using Labview program; process data • Monitor closely for errors at channels • Log events in a data text file • Proceed to Charge Injection Calibration Test phase. Bandele

15. Initial Function Test Sample data logged into text file Bandele

16. Charge Injection Calibration Test • Set and record pulse width and amplitude • Calculate expected output charge (area under pulse) • Inject charge to FE board/QIE generated by pulse generator • Run five consecutive events • Read and analyze data using Labview Software • Record Pulse Peak • Convert peak value from QIE code to charge value • Plot experimental results against expected charge value ME! Bandele

17. Charge Injection Calibration Test Bandele

18. Long Term Stability Test • Many boards are placed into Euro card crate • A looping acquisition is started. The acquisition counts the number of errors of each type on each board. • Test is run long enough to acquire enough statistics to be confident of the actual error rate. • This test is repeated with different groups of boards. Bandele

19. Long Term Stability Test Screenshot from the Tevatron IPM Labview program Bandele

20. Data Analysis - Calculation 15.0ns 5.22ns 4.56ns 5.22ns a b c 7.32V / 7.32 * 10-6A 4.56ns Voltage (V) = Current (I) * Resistance(R), Ohm’s Law I = V R 7.32V= I 1.3MΩ; 1.3MΩ = 1.3 * 106 Ω I = 7.32V 1.3 * 106 Ω =5.63 * 10-6A Area of Rectangle (Length * breath) = (4.56 * 10-9s) * (5.63 * 10-6A) = 25.6763 * 10-15C = 25.6763fC Area of Triangle {(1/2) * base * height} = {((5.22/2) * 10-9 s) * (5.63 * 10-6A)} =14.6943fC * 2 =29.3886fC Area under the curve (Expected charge value) = Area of Rectangle + Area of Triangle = 25.6763fC + 29.3886fC = 55.0649fC Bandele

21. Calibration Test - Data Conversion Table Screenshot from the Tevatron IPM Labview program Bandele

22. Calibration Test - Data Raw Data from Lab view Program Converted Data from Lab view Program Bandele

23. Calibration Test - Data 100kΩ 1MΩ 10MΩ Bandele

24. Gain Plots – Board #21 Bandele

25. Gain Plots – Board #23 Bandele

26. Conclusions • Difference in readings due to the variation in the experimental setup from advised specifications for QIE8 • Chip was originally designed to function at the Large Hadron Collider (LHC) at CERN • The clock integration period at which the QIE8 operates in Tevatron is 66ns (15.17MHz);should be 25ns (40MHz) • Longer clock integration time is necessary here at the Tevatron at Fermi Lab because of the difference in particle spacing • Bias resistance value of 750kΩ being used in the QIE circuitry, instead of the specified 220kΩ Bandele

27. Conclusion • Some channels on some test boards are dead • The majority of the channels have a similar linear transfer function, as expected • Most of the Front End Boards are good and can be used in Tevatron IPM Data Acquisition (DAQ) System Bandele

28. Future Works • There will be modifications made to several components of the channels • Boards will be re – tested until the desired result is attained Bandele

29. Acknowledgements • Almighty God • Dianne Engram • Dave Ritchie and Elliot McCrory, Mentors • Kwame Bowie – My Supervisor • Dr Davenport, Mentor • Particle Physics Division / Electrical Engineering Department Staff, 14th Floor • SIST Interns Bandele

30. QUESTIONS ? Bandele