Laser Tracking System (LTS)

1. Laser Tracking System (LTS) Son Nguyen Jassim Alshamali Aja Armstrong Matt Aamold

2. Presentation Outline • CDR Checklist • Digitization Sub-Systems • Controls Sub-Systems • Target Detection • Project Schedule

3. Slight Changes to Project • B/W sampling instead of Color • B/W uses intensity sampling • Color uses phase sampling from the back porch • Black background instead of white • Better laser detection • Two power supplies instead of one

4. CDR Checklist • Timing for digitization • Obtained main schematics • Functioning servos • Creating PWM design • Designing structure

5. Digitization Sub-System • Video Frame Timing • Video Line Timing • Sync Separator Outputs • State Machine Diagram • Timing Counters • Timing Schematic

6. Digitization – Video Frame Timing • Odd/Even Fields • Not every line in output of NTSC is valid data • Last line on each field is half line

7. Digitization – Video Line Timing • 63.5 us line time – not all is valid data • B/W is intensity based

8. Digitization – Sync Separator

9. Digitization – State Machine

10. Digitization – Timing Counters • Counter A – Divides 50Mhz to 12.5Mhz; sampling clock • Counter B - Throw out invalid lines; starts from line sync; 1,111,250ns @50Mhz = 55,562 cycles • Counter C – Throw out invalid line data; starts from Counter B; 9.4us @50Mhz = 470 cycles • Counter D – Sampling counter; starts from Counter C; 640 samples throughout 52.6us; Uses 12.5Mhz clock (Coordinate Counter A) • Counter E – Keeps track of which line in frame; 242 valid full lines (Coordinate Counter B)

11. Digitization – Timing Schematic

12. Controls Sub-System • Structure Design • Servo Testing • Pulse Wave Modulator Design • Power Supply Design

13. Controls - Structure • Rotary Base will serve as the x-axis • Designs for the y-axis movement are in progress

14. Controls - Servo Testing • Dual Timer Chip Used to Implement Hardware PWM • 50hz Base Signal Required • Changing the duty cycle changes the relative position of the servo

15. Controls - Servo Testing • HiTec HS-50 Servo • Full Counter-Clockwise 4.2% Duty Cycle • Full Clockwise 9.8% Duty Cycle • Center 7.0% Duty Cycle • Airnotics….Servo • Full Counter-Clockwise 3.2% Duty Cycle • Full Clockwise 9.8% Duty Cycle • Center 5.6% Duty Cycle

16. Controls - Pulse Wave Modulator Design • Pulse Wave Modulator (PWM) controls the duty cycle required to move the servos. • Implementation of the PWM will be on board the FPGA • Design of PWM will be designed in Verilog

17. Controls - Pulse Wave Modulator • PWM consists of several parts • Clock Divider to bring the 50Mhz clock of the FPGA down to 45hz-55hz for the base frequency of the PWM. • Verilog code to generate the behavior of a PWM • Accumulator and registers will be used to adjust the duty cycle of the 45hz-55hz waveform

18. Controls - Pulse Wave Modulator • The clock divider was made with flip flops to bring the frequency down to 47hz

19. Controls - Power Supply Design • Servos • 9 Volt unregulated transformer • With a 5 volt regulator • Digitizing Board • 12-15 Volt unregulated transformer • With 12 and 5 regulated voltages

20. Overall Power • Components • Camera • 12V * 200 mA = 2.4 Watts • Servos • Maximum of (9V-5V) * 1A = 4 Watts • All IC’s will go off of FPGA • FPGA will use a regulated 5V

21. Target Detection • Four main state machines • Target detector • Choosing mode • Static mode • Dynamic mode

22. State Machine for Target Detector

23. Project Schedule

24. Any Questions??