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Processor Design

Processor Design. Computer Architecture CS 215. CPU Design. CPU. Control Unit. Control Unit Generates the control signals in the correct order to effect the correct data path activity Data Path Set of interconnections and auxiliary registers

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Processor Design

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  1. Processor Design Computer ArchitectureCS 215

  2. CPU Design CPU Control Unit • Control Unit • Generates the control signals in the correct order to effect the correct data path activity • Data Path • Set of interconnections and auxiliary registers • Needed to accomplish overall changes an instruction makes Control signals out Control unit inputs Data Path

  3. 1-Bus Microarchitecture

  4. Abstract Vs. Concrete RTN How would accomplish the following instruction using this architecture? add(:=op=12)R[ra]R[rb]+R[rc]:

  5. Abstract Vs. Concrete RTN add(:=op=12)R[ra]R[rb]+R[rc]: Step RTN

  6. Abstract Vs. Concrete RTN:addi Step RTN T0. MA  PC: C  PC + 4; T1. MD  M[MA]; PC  C; T2. IR  MD; T3. A  R[rb]; T4. C  A + c2<16..0> {sign ext.}; T5. R[ra]  C;

  7. Abstract Vs. Concrete RTN:ld Step RTN T0-T2 Instruction fetch T3. A  (rb=0  0: rb0  R[rb]); T4. C  A + (16@IR<16>#IR<15..0>); T5. MA  C; T6. MD  M[MA]; T7. R[ra]  MD;

  8. Abstract Vs. Concrete RTN:st Step RTN T0-T2 Instruction fetch T3. A  (rb=0  0: rb0  R[rb]); T4. C  A + (16@IR<16>#IR<15..0>); T5. MA  C; T6. MD  R[ra]; T7. M[MA]  MD;

  9. Abstract Vs. Concrete RTN:br Step RTN T0-T2 Instruction fetch T3. CON  cond(R[rc]); T4. CON  PC  R[rb];

  10. Abstract Vs. Concrete RTN:shr Step Concrete RTN T0-T2 Instruction fetch T3. n  IR<4..0>; T4. (n=0)  (n  R[rc]<4..0>; T5. C  R[rb]; T6. Shr (:= (n≠0)(C<31..0>0#C<31..1>:n  n-1; Shr) ); T7. R[ra]  C;

  11. More Detail …

  12. General purpose registers Control signals 5x32 decoder More Detail … ra, rb, rc fields

  13. Try this! • Problem • Extend the SRC instruction set by adding the XOR command (op=19), similar to the AND commandNote: The ALU cannot be altered by adding XOR • Develop both an abstract and concrete RTN for the instruction

  14. Instruction Register

  15. Memory Interface

  16. ALU

  17. ALU

  18. Control sequences:Instruction Fetch Step Concrete RTN Control Sequence T0. MA  PC: C  PC+4; PCout, MAin, Inc4, Cin T1. MD  M[MA]: PC  C; Read, Cout, PCin, Wait T2. IR  MD; MDout, IRin T3. Instruction_execution

  19. Control sequences:add Step Concrete RTN Control Sequence T0. MA  PC: C  PC+4; PCout, MAin, Inc4, Cin, Read T1. MD  M[MA]: PC  C; Cout, PCin, Wait T2. IR  MD; MDout, IRin T3. A  R[rb]; Grb, Rout, Ain T4. C  A + R[rc]; Grc, Rout, ADD, Cin T5. R[ra]  C; Cout, Gra, Rin, End

  20. Control sequences:addi Step Concrete RTN Control Sequence T0. MA PC: C  PC + 4; PCout, MAin, Inc4, Cin T1. MD  M[MA]; PC  C; Cout, PCin, Wait, Read T2. IR  MD; MDout, IRin T3. A  R[rb]; Grb, Rout, Ain T4. C  A + c216..0 {sign ext.}; c2out, ADD, Cin T5. R[ra]  C; Cout, Gra, Rin, End

  21. Step Concrete RTN Control Sequence T0-T2 Instruction fetch Instruction fetch T3. A  (rb=0)  0: rb0  R[rb]; Grb, BAout, Ain T4. C  A + c216..0 {sign ext.}; c2out, ADD, Cin T5. MA  C; Cout, MAin T6. MD  R[ra]; Gra, Rout, MDin, Write T7. M[MA]  MD; Wait, End } address arithmetic Control sequences:st

  22. Control sequences:shr • Step Concrete RTN Control Sequence • T0-T2 Instruction fetch Instruction fetch • T3. n  IR4..0; c1out, Ld • T4. (n=0)  (n  R[rc]4..0); n=0  (Grc, Rout, Ld) • T5. C  R[rb]; Grb, Rout, C=B, Cin • T6. Shr (:=(n≠0) n0  (Cout, SHR, Cin, • (C31..0 0#C31..1: Decr, Goto6) • n  n-1; Shr) ); • T7. R[ra]  C; Cout, Gra, Rin, End

  23. Control sequences:br Step Concrete RTN Control Sequence T0-T2 Instruction fetch Instruction fetch T3. CON  cond(R[rc]); Grc, Rout, CONin T4. CON  PC  R[rb]; Grb, Rout, CON  PCin, End

  24. Clocking & Timing

  25. Control Unit

  26. 2-Bus SRC

  27. 3-Bus SRC

  28. From a need to initialize processor to a known, defined state Control Step Counter  0 PC  Known Value RTN instruction_interpretation := (RunStrt  (Run  1: PC, R[0..31]  0); RunRst (IR  M[PC]: PC  PC + 4;instruction_execution): RunRst  ( Rst  0: PC  0); instruction_interpretation): Machine Reset

  29. Types of Exceptions • System Reset • Machine Check Exceptions • Memory error checking • Data Access Exceptions • Instruction Access Exceptions • Alignment Exceptions

  30. Types of Exceptions • Program Exceptions • Illegal instruction • Unimplemented instruction • Privileged instruction • Arithmetic errors (sometimes)

  31. Types of Exceptions • Miscellaneous Hardware Exceptions • Countdown to zero • Trace & Debugging Exceptions • Nonmaskable Exceptions • Cannot be ignored • Power outage • Interrupts (External)

  32. Exception Process • Interrupt signal asserted • Determine if interrupt should be serviced; Finish current instruction, if possible

  33. Exception Process instruction_interpretation := (RunStrt  Run  1: Run(ireqIE)  (IR M[PC]: PC  PC + 4; instruction_execution): Run(ireqIE)  (IPC  PC31..0: II15..0Isrc_info15..0: iack 1: IE 0: PC  Ivect31..0; iack  0); instruction_interpretation);

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