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ECE 448 Lecture 13

ECE 448 Lecture 13. Memories: RAM, ROM. Generic Memories. Generic RAM (1). LIBRARY ieee; USE ieee.std_logic_1164.all; ------------------------------------------------------------------------------------------------- ENTITY ram IS

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ECE 448 Lecture 13

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  1. ECE 448 Lecture 13 Memories: RAM, ROM ECE 448 – FPGA and ASIC Design with VHDL

  2. Generic Memories ECE 448 – FPGA and ASIC Design with VHDL

  3. Generic RAM (1) LIBRARY ieee; USE ieee.std_logic_1164.all; ------------------------------------------------------------------------------------------------- ENTITY ram IS GENERIC (bits: INTEGER:=8; -- # of bits per word words: INTEGER := 16); -- # of words in the memory PORT (wr_ena, clk: IN STD_LOGIC; addr: IN INTEGER RANGE 0 to words-1; data_in: IN STD_LOGIC_VECTOR(bits -1 downto 0); data_out: OUT STD_LOGIC_VECTOR(bits – 1 downto 0) ); END ram; ECE 448 – FPGA and ASIC Design with VHDL

  4. Generic RAM – inferring LUT-based RAM (2) ARCHITECTURE LUT_based_ram OF ram IS TYPE vector_array IS ARRAY (0 TO words-1) OF STD_LOGIC_VECTOR(bits – 1 DOWNTO 0); SIGNAL memory: vector array; BEGIN PROCESS(clk, addr) BEGIN IF(wr_ena=‘1’) THEN IF (rising_edge(clk)) THEN memory(addr) <= data_in; END_IF; END IF; END PROCESS; data_out <= memory(addr); END LUT_based_RAM; ECE 448 – FPGA and ASIC Design with VHDL

  5. Generic RAM – inferring Block RAM (2) ARCHITECTURE LUT_based_ram OF ram IS TYPE vector_array IS ARRAY (0 TO words-1) OF STD_LOGIC_VECTOR(bits – 1 DOWNTO 0); SIGNAL memory: vector array; BEGIN PROCESS(clk) BEGIN IF(wr_ena=‘1’) THEN IF (rising_edge(clk)) THEN memory(addr) <= data_in; END_IF; END IF; IF rising_edge(clk) THEN data_out <= memory(addr); END IF; END PROCESS; END LUT_based_RAM; ECE 448 – FPGA and ASIC Design with VHDL

  6. Generic ROM (1) LIBRARY ieee; USE ieee.std_logic_1164.all; ------------------------------------------------------------------------------------------------- ENTITY rom IS GENERIC (bits: INTEGER:=8; -- # of bits per word words: INTEGER := 8); -- # of words in the memory PORT ( addr: IN INTEGER RANGE 0 TO words-1; data: OUT STD_LOGIC_VECTOR(bits – 1 DOWNTO 0) ); END rom; ECE 448 – FPGA and ASIC Design with VHDL

  7. Generic ROM (2) ARCHITECTURE behavioral OF rom IS TYPE vector_array IS ARRAY (0 TO words-1) OF STD_LOGIC_VECTOR(bits – 1 DOWNTO 0); CONSTANT memory: vector_array := ("0000_0000", "0000_0010", "0000_0100", "0000_1000", "0001_0000", "0010_0000", "0100_0000", "1000_0000"); BEGIN data <= memory(addr); END rom; ECE 448 – FPGA and ASIC Design with VHDL

  8. Generic ROM (3) – hexadecimal notation ARCHITECTURE behavioral OF rom IS TYPE vector_array IS ARRAY (0 TO words-1) OF STD_LOGIC_VECTOR(bits – 1 DOWNTO 0); CONSTANT memory: vector_array := (X"00", X"02", X"04", X"08", X"10", X"20", X"40", X"80"); BEGIN data <= memory(addr); END rom; ECE 448 – FPGA and ASIC Design with VHDL

  9. FPGA specific memories ECE 448 – FPGA and ASIC Design with VHDL

  10. Distributed RAM RAM16X1S D WE WCLK = O A0 A1 A2 A3 LUT LUT LUT RAM32X1S D WE WCLK A0 O A1 A2 A3 A4 or RAM16X2S D0 D1 WE = WCLK O0 A0 O1 RAM16X1D A1 A2 D A3 WE or WCLK A0 SPO A1 A2 A3 DPRA0 DPO DPRA1 DPRA2 DPRA3 • CLB LUT configurable as Distributed RAM • A LUT equals 16x1 RAM • Implements Single and Dual-Ports • Cascade LUTs to increase RAM size • Synchronous write • Synchronous/Asynchronous read • Accompanying flip-flops used for synchronous read ECE 448 – FPGA and ASIC Design with VHDL

  11. RAM 16x1 (1) library IEEE; use IEEE.STD_LOGIC_1164.all; library UNISIM; use UNISIM.all; entity RAM_16X1_DISTRIBUTED is port( CLK : in STD_LOGIC; WE : in STD_LOGIC; ADDR : in STD_LOGIC_VECTOR(3 downto 0); DATA_IN : in STD_LOGIC; DATA_OUT : out STD_LOGIC ); end RAM_16X1_DISTRIBUTED; ECE 448 – FPGA and ASIC Design with VHDL

  12. RAM 16x1 (2) architecture RAM_16X1_DISTRIBUTED_STRUCTURAL of RAM_16X1_DISTRIBUTED is -- part used by the synthesis tool, Synplify Pro, only; ignored during simulation attribute INIT : string; attribute INIT of ram16x1s_1: label is "0000"; ------------------------------------------------------------------------ component ram16x1s generic( INIT : BIT_VECTOR(15 downto 0) := X"0000"); port( O : out std_ulogic; A0 : in std_ulogic; A1 : in std_ulogic; A2 : in std_ulogic; A3 : in std_ulogic; D : in std_ulogic; WCLK : in std_ulogic; WE : in std_ulogic); end component; ECE 448 – FPGA and ASIC Design with VHDL

  13. RAM 16x1 (3) begin ram16x1s_1: ram16x1s generic map (INIT => X”0000") port map (O => DATA_OUT, A0 => ADDR(0), A1 => ADDR(1), A2 => ADDR(2), A3 => ADDR(3), D => DATA_IN, WCLK => CLK, WE => WE ); end RAM_16X1_DISTRIBUTED_STRUCTURAL; ECE 448 – FPGA and ASIC Design with VHDL

  14. ROM 16x1 (1) library IEEE; use IEEE.STD_LOGIC_1164.all; library UNISIM; use UNISIM.all; entity ROM_16X1_DISTRIBUTED is port( ADDR : in STD_LOGIC_VECTOR(3 downto 0); DATA_OUT : out STD_LOGIC ); end ROM_16X1_DISTRIBUTED; ECE 448 – FPGA and ASIC Design with VHDL

  15. ROM 16x1 (2) architecture ROM_16X1_DISTRIBUTED_STRUCTURAL of ROM_16X1_DISTRIBUTED is attribute INIT : string; attribute INIT of rom16x1s_1: label is "F0C1"; component ram16x1s generic( INIT : BIT_VECTOR(15 downto 0) := X"0000"); port( O : out std_ulogic; A0 : in std_ulogic; A1 : in std_ulogic; A2 : in std_ulogic; A3 : in std_ulogic; D : in std_ulogic; WCLK : in std_ulogic; WE : in std_ulogic); end component; signal Low : std_ulogic := ‘0’; ECE 448 – FPGA and ASIC Design with VHDL

  16. ROM 16x1 (3) begin rom16x1s_1: ram16x1s generic map (INIT => X"F0C1") port map (O=>DATA_OUT, A0=>ADDR(0), A1=>ADDR(1), A2=>ADDR(2), A3=>ADDR(3), D=>Low, WCLK=>Low, WE=>Low ); end ROM_16X1_DISTRIBUTED_STRUCTURAL; ECE 448 – FPGA and ASIC Design with VHDL

  17. std_logic vs. std_ulogic TYPE std_ulogic IS (‘U’, ‘X’, ‘0’, ‘1’, ‘Z’, ‘W’, ‘L’, ‘H’, ‘-’); SUBTYPE std_logic IS std_ulogic RANGE ‘X’ TO ‘-’; ECE 448 – FPGA and ASIC Design with VHDL

  18. Conversion std_logic_vector => integer (1) LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_arith.all; entity test is end test; architecture behavior of test is SIGNAL stdl_addr: STD_LOGIC_VECTOR(7 DOWNTO 0); SIGNAL u_addr: UNSIGNED(7 DOWNTO 0); SIGNAL i_addr : INTEGER; begin u_addr <= unsigned(stdl_addr); i_addr <= conv_integer(u_addr); end behavior; ECE 448 – FPGA and ASIC Design with VHDL

  19. Conversion std_logic_vector => integer (2) LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_arith.all; entity test is end test; architecture behavior of test is SIGNAL stdl_addr: STD_LOGIC_VECTOR(7 DOWNTO 0); SIGNAL i_addr : INTEGER; begin u_addr <= conv_integer(unsigned(stdl_addr)); end behavior; ECE 448 – FPGA and ASIC Design with VHDL

  20. Instruction ROM example (1) LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_arith.all; ENTITY instruction_rom IS GENERIC ( w : INTEGER := 16; n : INTEGER := 8; m : INTEGER := 3); PORT ( Instr_addr : IN STD_LOGIC_VECTOR(m-1 DOWNTO 0); Instr : out STD_LOGIC_VECTOR(w-1 DOWNTO 0) ); END instruction_rom; ECE 448 – FPGA and ASIC Design with VHDL

  21. Instruction ROM example (2) ARCHITECTURE ins_rom OF insstruction_rom IS SIGNAL temp: INTEGER RANGE 0 TO 7; TYPE vector_array IS ARRAY (0 to n-1) OF STD_LOGIC_VECTOR(w-1 DOWNTO 0); CONSTANT memory : vector_array := ( "0000_0000_0000_0000", "0000_0000_0000_0000", "1101_0100_0101_1001", "1101_0100_0101_1000", "0110_1000_1000_0111", "0100_1001_1001_1010", "1111_0110_0111_0101", "1111_0110_0111_0100", BEGIN temp <= conv_integer(unsigned(Instr_addr)); Instr <= memory(temp); END instruction_rom; ECE 448 – FPGA and ASIC Design with VHDL

  22. Generic dual-ported memory (1) LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_arith.all; ENTITY memory_local IS PORT( wen : IN STD_LOGIC; clk : IN STD_LOGIC; data_in : IN STD_LOGIC_VECTOR(31 DOWNTO 0); addr1 : IN STD_LOGIC_VECTOR(4 DOWNTO 0); addr2 : IN STD_LOGIC_VECTOR (4 DOWNTO 0); data_out1: OUT STD_LOGIC_VECTOR(31 DOWNTO 0); data_out2: OUT STD_LOGIC_VECTOR(31 DOWNTO 0) ); END memory_local; ECE 448 – FPGA and ASIC Design with VHDL

  23. Generic dual-ported memory (2) ARCHITECTURE memory_local OF memory_local IS TYPE vector_array IS ARRAY (0 TO 31) OF STD_LOGIC_VECTOR(31 DOWNTO 0); SIGNAL memory : vector_array; SIGNAL temp1: INTEGER RANGE 0 TO 31; SIGNAL temp2: INTEGER RANGE 0 TO 31; BEGIN temp1 <= conv_integer(unsigned(addr1)); temp2 <= conv_integer(unsigned(addr2)); PROCESS(clk, temp1, temp2) BEGIN IF (wen = '1') THEN IF (clk = '1' AND clk'event) THEN memory(temp2) <= data_in; END IF; END IF; END PROCESS; data_out1 <= memory(temp1); data_out2 <= memory(temp2); END memory_local; ECE 448 – FPGA and ASIC Design with VHDL

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