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Pipelining FAQ

1. What is pipelining?. Ans: Computer design technique to increase instruction throughput. Individual instructions are not sped up. Instead batches of instructions are more efficiently executed. . Execution time of pipelined and non-pipelined computer for a single instruction is the same.When e

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Pipelining FAQ

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    1. Pipelining FAQ Alex Jay CS 147 F07

    2. 1. What is pipelining? Ans: Computer design technique to increase instruction throughput. Individual instructions are not sped up. Instead batches of instructions are more efficiently executed.

    3. Execution time of pipelined and non-pipelined computer for a single instruction is the same. When executing multiple instructions, pipelining decreases the speed of the entire job. 1. What is pipelining?

    4. 2. How does it work? As each instruction moves through the pipeline stages, the next instruction is moved into the vacated pipeline stage Ideally, each stage in a pipelined system takes an equal amount of time to complete.

    5. 5 stage pipeline IF = instruction fetch, ID = instruction decode, EX = execute, MEM = memory acces, WB = register write back 2. How does it work?

    6. 3. What are the performance gains? Speedup: the ratio of the average non-pipelined instruction execution time per average pipelined execution time.

    7. 3. What are the performance gains?

    8. 3. What are the performance gains?

    9. 3. What are the performance gains?

    10. 3. What are the performance gains?

    11. Non-pipelined design prevents branch delays. This makes them easier and cheaper to make. Instruction latency is higher in pipelined designs because of added flip flops into the data path. 4. What are the disadvantages?

    12. 4. What are the disadvantages? Pipeline hazards. Structural: The simultaneous use of the same resources. Control: Program branches and overall flow. Data: Data dependencies between instructions.

    14. 5. Solutions to hazards Software inserted No-Ops into the instructions. Hardware inserted Stalls. Similar to No-ops. Branch prediction schemes. Assume a correct path and prefetch that instruction branch. ( can have up to 90% efficiency)

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