1 / 15

Module 6: Multi-Gb/s Signaling Topic 4: Modulation

Module 6: Multi-Gb/s Signaling Topic 4: Modulation. OGI EE564 Howard Heck. Where Are We? . Introduction Transmission Line Basics Analysis Tools Metrics & Methodology Advanced Transmission Lines Multi-Gb/s Signaling Projections, Limits, & Barriers Differential Signaling Clocking Issues

nicolette
Download Presentation

Module 6: Multi-Gb/s Signaling Topic 4: Modulation

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript


  1. Module 6: Multi-Gb/s SignalingTopic 4: Modulation OGI EE564 Howard Heck Section 6.4

  2. Where Are We? • Introduction • Transmission Line Basics • Analysis Tools • Metrics & Methodology • Advanced Transmission Lines • Multi-Gb/s Signaling • Projections, Limits, & Barriers • Differential Signaling • Clocking Issues • Equalization Techniques • Modulation Techniques • Special Topics Section 6.4

  3. Contents • Modulation/Encoding • Pulse Amplitude Modulation • Pulse Width Modulation • Multi-Carrier Modulation • Simultaneous Bi-directional Signaling • Summary • References Section 6.4

  4. Amplitude Modulation Intro Simplest form is binary signaling: • Maps all of the possible voltage levels into one of two values (“0” or “1”), as shown here: • Vmin and Vmax denote the minimum and maximum voltage levels. • V0 and V1 represent the “nominal” voltages for the “0” and “1” symbols. • Vthresh is the threshold that separates the two binary values. • Note: the levels could have any arbitrary value. • Also known as pulse amplitude modulation (PAM) or multi-level signaling Section 6.4

  5. N-PAM Signaling • We can encode a set of N symbols on a continuous variable, V, where . • Assign each symbol a nominal value . [9.2.1] • Define N-1 thresholds . [9.2.2] • Example: 4 PAM Section 6.4

  6. PAM Transfer Rate • The effective transfer rate (bits/sec) is [9.2.3] TR = transfer rate (bits/sec) m = # of signal levels f = operating frequency [Hz] Section 6.4

  7. Why Use PAM? PAM may be beneficial when: • Channel has severe bandwidth roll off (D>6) • Channel has high SNR in passband • Circuits are symbol rate limited Requirements & trade-offs: • Reduced swings (SNR) • More complex circuitry (cost) • Increased latency (encoding and decoding) Section 6.4

  8. Pulse Width Modulation (PWM) Intro • To use PWM, we must encode the data into pulse widths. To code m data bits, we need n edges: [9.2.4] T = Minimum pulse width. Limited by interconnect bandwidth. t = Edge placement capability. Limited by interconnect & circuit jitter. • Transfer rate: [9.2.5] Section 6.4

  9. PWM Performance Trends Section 6.4

  10. PWM Spectral Comparison for a 10 Gb/s Example NRZ • 1 bit/symbol PWM • 100 ps symbol width Example Waveforms PWM • 4 bits/symbol • 20 ps edge separation • 16 edge positions • 400 ps symbol width Power Spectrum Cumulative Power Spectrum Section 6.4

  11. Simultaneous Bi-Directional Signaling • Also known as Full Duplex Signaling. • Goal: double the effective transfer rate by sending bits simultaneously in both directions. • What happens when one agent drives high while the other drives low? • Assuming the drivers are of equal strength, the line gets pulled to ½VCC. We must have a way to handle this situation. • We’ll do it by using our knowledge of the state of the driver to adjust the switching threshold of the receiver. Section 6.4

  12. Simultaneous Bi-Directional Signaling #2 • The reference generator circuits use the output signal to dynamically adjust the (-) input to the receiver, as shown in the table below: Section 6.4

  13. SBD Trade-offs Requirements: • Near perfect termination • Minimized reference voltage noise • Added I/O complexity • consumes more area on the silicon (cost) • more difficult to test (cost) Section 6.4

  14. Summary Section 6.4

  15. References General • W. Dally and J. Poulton, Digital Systems Engineering, Chapters 4.3 & 11, Cambridge University Press, 1998. • S. Dabral and T. Maloney, Basic ESD and I/O Design, Wiley Interscience, New York, 1998, ISBN 0-471-25359-6. Section 6.4

More Related