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ECEN 248: INTRODUCTION TO DIGITAL SYSTEMS DESIGN

ECEN 248: INTRODUCTION TO DIGITAL SYSTEMS DESIGN. Lecture 7 Dr. Shi Dept. of Electrical and Computer Engineering. BINARY ADDERS. Overview. Addition of binary data is fundamental Need to determine hardware implementation Represent inputs and outputs Inputs: single bit values, carry in

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ECEN 248: INTRODUCTION TO DIGITAL SYSTEMS DESIGN

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  1. ECEN 248: INTRODUCTION TO DIGITAL SYSTEMS DESIGN Lecture 7 Dr. Shi Dept. of Electrical and Computer Engineering

  2. BINARY ADDERS

  3. Overview • Addition of binary data is fundamental • Need to determine hardware implementation • Represent inputs and outputs • Inputs: single bit values, carry in • Outputs: Sum, Carry • Hardware features • Create a single-bit adder and chain together • Dealing with overflow • What happens if numbers are too big?

  4. 4-Bit Adder Think top-down: How to break a problem into pieces?

  5. A3 A2 A1 A0 B3 B2 B1 B0 0 1 0 1 0 1 1 1 A B Ci+1 Ci 0 1 0 1 0 1 1 1 1 1 1 Ai +Bi A B Si 1 1 0 0 Multiple-bit Addition Consider single-bit adder for each bit position. Each bit position creates a sum and carry

  6. Block Diagram Full Adder Single-bit full adder, building block of large adders Common piece of computer hardware

  7. AiBi Ci Ai Bi Si Ci+1 00 01 11 10 Ci 0 0 0 0 0 0 0 1 1 0 0 1 0 1 0 0 1 1 0 1 1 0 0 1 0 1 0 1 0 1 1 1 0 0 1 1 1 1 1 1 1 1 0 1 1 1 Si Full Adder Full adder includes carry in Ci Notice interesting pattern in Karnaugh map.

  8. AiBi Ci Ai Bi Si Ci+1 00 01 11 10 Ci 0 0 0 0 0 0 0 1 1 0 0 1 0 1 0 0 1 1 0 1 1 0 0 1 0 1 0 1 0 1 1 1 0 0 1 1 1 1 1 1 1 0 1 1 1 1 Ci+1 Full Adder Now consider implementation of carry out Two outputs per full adder bit (Ci+1, Si) Note: 3 inputs

  9. Full Adder Implementation Si = Ci(Ai Bi) Ci+1 = Ai · Bi + Ci · (Ai Bi)

  10. Full Adder Hardware repetition simplifies hardware design A full adder can be made from two half adders (plus an OR gate).

  11. C 1 1 1 0 A 0 1 0 1 B0 1 1 1 S 1 1 0 0 4-Bit Adder Chain single-bit adders together. What does this do to delay?

  12. S C A B 0 0 0 1 A 0 S 0 0 0 0 0 1 1 0 1 0 1 0 1 1 0 1 0 B 0 C 1 Dec Binary 1 1 +1 +1 2 10 Half Adder (not very useful) • Add two binary numbers • A0 , B0 -> single bit inputs • S0 -> single bit sum • C1 -> carry out

  13. Multiplexers

  14. Multiplexers • Select an input value with one or more select bits • Use for transmitting data • Allows for conditional transfer of data • Sometimes called a mux

  15. 4– to– 1- Line Multiplexer

  16. Quadruple 2–to–1-Line Multiplexer Notice enable bit Notice select bit 4 bit inputs

  17. Multiplexer as combinational modules • Connect input variables to select inputs of multiplexer (n-1 for n variables) • Set data inputs to multiplexer equal to values of function for corresponding assignment of select variables • Using a variable at data inputs reduces the size of the multiplexer

  18. Implementing a Four- Input Function with a Multiplexer

  19. Multiplexers & Shannon Expansion

  20. Shannon Expansion Theorem • The Shannon expansion develops the idea that Boolean functions can be reduced by means of the identity: • where F is any function and Fx and Fx' are Shannon cofactors of F.

  21. Example f = yz + xyz' + x'y'z = yz(x' + x) + xyz' + x'y'z = x'yz + xyz + xyz' + x'y'z = x'(yz + y'z) + x(yz + yz') = x'gx' + xgx

  22. Expand about 2 variables

  23. Multiplexer Implementation

  24. DECODERS

  25. Overview • Binary decoders • Converts an n-bit code to a single active output • Can be developed using AND/OR gates • Can be used to implement logic circuits. • Binary encoders • Converts one of 2n inputs to an n-bit output • Useful for compressing data • Can be developed using AND/OR gates • Both encoders and decoders are extensively used in digital systems

  26. Binary Decoder • Black box with n input lines and 2n output lines • Only one output is a 1 for any given input Binary Decoder n inputs 2n outputs Enable

  27. F0 = X'Y'E F1 = X'YE F2 = XY'E F3 = XYE X Y 2-to-4 Binary Decoder Truth Table: • From truth table, circuit for 2x4 decoder is: • Note: Each output is a 2-variable minterm (X'Y', X'Y, XY' or XY) Enable = 1 Enable F0 F1 F2 F3 2-to-4 Decoder X Y Enable

  28. F0 = x'y'z’E F1 = x'y'zE F2 = x'yz'E F3 = x'yzE F4 = xy'z'E F5 = xy'zE F6 = xyz'E F7 = xyzE x y z 3-to-8 Binary Decoder Truth Table: Enable = 1 F0 F1 F2 F3 F4 F5 F6 F7 X 3-to-8 Decoder Y Z Enable Enable

  29. Implementing Functions Using Decoders • Any n-variable logic function can be implemented using a single n-to-2n decoder to generate the minterms • OR gate forms the sum. • The output lines of the decoder corresponding to the minterms of the function are used as inputs to the or gate. • Any combinational circuit with n inputs and m outputs can be implemented with an n-to-2n decoder with m OR gates. • Suitable when a circuit has many outputs, and each output function is expressed with few minterms.

  30. Implementing Functions Using Decoders • Example: Full adder S(x, y, z) = S (1,2,4,7) C(x, y, z) = S (3,5,6,7) Enable = 1 3-to-8 Decoder 0 1 2 3 4 5 6 7 S x S2 S1 S0 y C z Enable

  31. Use two 3 to 8 decoders to make 4 to 16 decoder • In this example, only one decoder can be active at a time. • x, y, z effectively select output line for w

  32. Encoders

  33. Binary encoder 2n inputs n outputs . . . . . . Encoders • If the a decoder's output code has fewer bits than the input code, the device is usually called an encoder. e.g. 2n-to-n • The simplest encoder is a 2n-to-n binary encoder • One of 2n inputs = 1 • Output is an n-bit binary number

  34. Inputs Outputs I I I I I I I I y2 y1 y0 0 1 2 3 4 5 6 7 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 1 0 I0 I1 I2 I3 I4 I5 I6 I7 0 0 0 1 0 0 0 0 0 1 1 0 0 0 0 1 0 0 0 1 y2 = I4 + I5 + I6 + I7 y1 = I2 + I3 + I6 + I7 y0 = I1 + I3 + I5 + I7 8-to-3 Binary Encoder At any one time, only one input line has a value of 1. 0 0 0 0 0 0 0 1 0 0 1 0 1 0 0 0 0 0 0 1 0 1 1 0 0 0 0 0 0 0 0 1 1 1 1

  35. Inputs Outputs I I I I I I I I y2 y1 y0 Idle 0 1 2 3 4 5 6 7 0 0 0 0 0 0 0 0 x x x 0 1 0 0 0 0 0 0 0 0 0 0 1 X 1 0 0 0 0 0 0 0 0 1 1 X X 1 0 0 0 0 0 0 1 0 1 X X X 1 0 0 0 0 0 1 1 1 X X X X 1 0 0 0 1 0 0 1 X X X X X 1 0 0 1 0 1 1 X X X X X X X X X X X X X 1 0 1 1 1 1 1 1 1 0 1 8-to-3 Priority Encoder • What if more than one input line has a value of 1? • Ignore “lower priority” inputs. • Idle indicates that no input is a 1.

  36. Inputs Outputs I I I I I I I I y2 y1 y0 Idle 0 1 2 3 4 5 6 7 0 0 0 0 0 0 0 0 x x x 0 1 0 0 0 0 0 0 0 0 0 0 1 X 1 0 0 0 0 0 0 0 0 1 1 X X 1 0 0 0 0 0 0 1 0 1 X X X 1 0 0 0 0 0 1 1 1 X X X X 1 0 0 0 1 0 0 1 X X X X X 1 0 0 1 0 1 1 X X X X X X X X X X X X 1 X 0 1 1 1 1 1 0 1 1 1 Priority Encoder (8 to 3 encoder) • Priority Encoder :H7=I7 (Highest Priority) H6=I6·I7’ H5=I5·I6’ ·I7’ H4=I4·I5’ ·I6’·I7’ H3=I3.I4’·I5’ ·I6’·I7’ H2=I2.I3’·I4’ ·I5’·I6’ ·I7’ H1=I1· I2’ ·I3’·I4’ · I5’·I6’ ·I7’ H0=I0·I1’ ·I2’·I3’ ·I4’ ·I5’ ·I6’ ·I7’ IDLE= I0’ ·I1’ · I2’ ·I3’ ·I4’ ·I5’ ·I6’ ·I7’ I0 H0 I1 H1 I2 H2 I3 H3 I4 H4 I5 H5 I6 H6 I7 H7 IDLE

  37. Priority Encoder (8 to 3 encoder) • Assign priorities to the inputs • When more than one input are asserted, the output generates the code of the input with the highest priority • Priority Encoder :H7=I7 (Highest Priority) H6=I6·I7’ H5=I5·I6’ ·I7’ H4=I4·I5’ ·I6’·I7’ H3=I3.I4’·I5’ ·I6’·I7’ H2=I2.I3’·I4’ ·I5’·I6’ ·I7’ H1=I1· I2’ ·I3’·I4’ · I5’·I6’ ·I7’ H0=I0·I1’ ·I2’·I3’ ·I4’ ·I5’ ·I6’ ·I7’ IDLE= I0’ ·I1’ · I2’ ·I3’ ·I4’ ·I5’ ·I6’ ·I7’ • Encoder Y0 = I1 + I3 + I5 + I7 Y1 = I2 + I3 + I6 + I7 Y2 = I4 + I5 + I6 + I7 Priority encoder Priority Circuit Binary encoder I0 I0 H0 I0 I1 I1 H1 I1 Y0 I2 I2 H2 I2 Y0 Y1 I3 I3 H3 I3 Y1 Y2 I4 I4 H4 I4 Y2 I5 I5 H5 I5 I6 I6 H6 I6 I7 I7 H7 I7 IDLE IDLE

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