Acquisition Crate Design

1. Acquisition Crate Design BI Technical Board 26 August 2011 Beam Loss Monitoring Section William Vigano’ william.vigano@cern.ch

2. Acquisition Crate Design Philosophy The design philosophy is the following: • Performance Improving • System Reliability • Protection and Current Limiting • Total separation between System Functionality and System Safety Functions • Remote Diagnosis • Remote control and calibration william.vigano@cern.ch

3. Acquisition Crate Extract by the 3D model of the Acquisition Crate william.vigano@cern.ch

4. BLEDP BLEDP – Cards (Analog Front End) william.vigano@cern.ch

5. BLEDP – Block Diagram Available Resources: 8 Input Analog Interfaces; FPGA local or remote programming; bidirectional optical link; power supplies with protection and diagnosis; temperature and humidity measurement; ID Chip; auxiliary Ethernet link for diagnosis; Auxiliary ADC for Housekeeping Monitor. william.vigano@cern.ch

6. Shielded Box SFP - Transceiver BLEDP Mixed Connector -> 24 pin + 8 Coaxial inserts High Reliability Dc/Dc Converters william.vigano@cern.ch

7. BLEDP - Analog Front End principle The new analog Front End input channel is based on matching two principles: • Advanced Current to Frequency converter (it is a fully differential Front End based on Giuseppe Venturini’s proposal for the CERN ASIC) • Direct Acquisition (using the fast ADC capability for the current measurement on the input shunt) Data Output Input from the Monitor DADC ACFC Reset Interface Calibration Interface william.vigano@cern.ch

8. ACFC Principle Input switch Fully differential Integrator A status signal selects in which branch of a fully deferential stage the input current is integrated. Two comparators check the deferential output voltage against a threshold, whenever is exceeded, the status signal changes to the complementary value (0 ! 1 or 1 ! 0) and the input current is integrated in the other branch. william.vigano@cern.ch

9. DADC Principle Input 50 ohm resistor split in two: 47 + 3 ohm Re-routing on the ADC buffer amplifier william.vigano@cern.ch

10. Analog Front End Block Diagram The two different measurement principles are implemented in a machine able to use the same components but connected in a different way. Some switches in the circuit allow commutation from ACFC to DADC and the opposite. william.vigano@cern.ch

11. ACFC & DADC • The input channel circuit is able to measure current input from 10pA to 200mA. • The measurement of the current input is performed by two different techniques: • Advanced Current to Frequency Converter (ACFC) used in the range 10pA to 30mA • Direct ADC acquisition (DADC) used in the range 20.3µA to 200mA • The passage between the 2 ranges is managed by the FPGA. • When the FPGA measures the maximum ACFC counts, it switches the circuit to the modality DADC. • When the value of the DADC returns below a threshold, the FPGA switches the circuit to the ACFC modality. william.vigano@cern.ch

12. Analog Crate Calibration All the Channels of all the Cards in the CRATE can be calibrated from remote with the same current reference (Internal or External) • Parameters settable remotely: • Analog Comparator Threshold (Digital potentiometer value – channel A) • Offset Current (Digital potentiometer value – channel B) • Measurement Period • Current Source available on the Backplane with precision 2% • Current Source available external with precision 0.1% BLEDP Input Channel Internal Flash Memory Monitor Input Input Selector Optical Transceiver Current Source 48Vdc Analog Comparator Threshold Offset Current Backplane Mezzanine william.vigano@cern.ch

13. Power Supply Presence LEDs Status of Calibration Relays Main Switch Input connector for external Current Source Main Panel william.vigano@cern.ch

14. CRATE Power Supply The Main Power Supply will be integrated in the CRATE, maintaining the possibility to be replaced in 1 working hour. It generates a common voltage bus of 48 Volts for all the cards in order tolimitthe current flowing on the backplane, optimizing in the meantime the ripple noise. william.vigano@cern.ch

15. Power Supply Structure Block Diagram Circuit Breakers Main Power Supply Local creation of all required voltages in the BLEDP Cards william.vigano@cern.ch

16. Backplane • The Backplane will manage the following functions: • Monitor input wiring • 48Vdc Power Distribution and protection by Resettable Fuses • Internal Current Source • Relays Multiplexer for Calibration of all the channels with the same current william.vigano@cern.ch

17. The BLECU is a Controller Card. It will be implemented in a second stage of the project to improve the functionalities of the Backplane. • It will manage the following functions: • Detection of the current break for the 48V lines • Global CRATE current consumption measurement • Remote On/Off of the BLEDP Cards • Current Source selection (Internal/External) • Current Value selection for the Internal Current Source • CRATE Temperature and Humidity measurement (Sensor mounted on the Backplane) • CRATE Identifier chip readout (Chip mounted on the Backplane) BLECU william.vigano@cern.ch

18. Simulation Models PSPICE Models were create to simulate several working conditions like worst case, Monte Carlo analysis, extreme performance. Current Source PSPICE Model BLEDP Analog Input Interface PSPICE Model Dc/Dc Converter – TI SwitcherPro Model The BLEDP Analog Input Interface PSPICE model allows to verify and evaluate all the circuit delay errors, input leakage current and signal distortion. william.vigano@cern.ch

19. Prototype Verification Prototypes have been created to verify the BLEDP Analog Input Interface and the Current Source Current Source BLEDP Analog Input Interface william.vigano@cern.ch

20. Prototype Results The BLEDP Analog Input Interface Prototype allow to measure the current in the range: 3 pA ÷ 200mA Better evaluation of performances will be done with the BLEDP PCB (currently in the design and manufacturing phase) william.vigano@cern.ch

21. Thank you for your attention william.vigano@cern.ch