A Case Study of the Rehosting from VHDL to Matlab/C

1. A Case Study of the Rehosting from VHDL to Matlab/C Presenter: Yulong Zou Stevens Institute of Technology Sep. 2, 2010 1

2. Outline • Basic Structure of a VHDL Code • Challenging Issues and Solutions to the VHDL Rehosting • A Case Study of the VHDL Rehosting for an ADDER • Next Step 2

3. Basic Structure of a VHDL Code 3 In VHDL, a digital system consists of a design entity that can contain other entities that are then considered components by the top-level entity. Each entity is typically modeled by an entity declaration and an architecture, as shown below:

4. A General Entity Declaration Form 4 • Entity Declaration (Interface): It defines the NAME of the entity and lists the input and output ports. The general form is shown as follows, entity NAME_OF_ENTITY is port (signal_names: modetype; signal_names: modetype; : signal_names: mode type); end [NAME_OF_ENTITY] ;

5. A General Architecture Body Description 5 • Architecture (Body): This specifies how a digit circuit operates and how it is implemented. A general form of an architecture body is described as, architecture architecture_name of NAME_OF_ENTITY is -- Declarations -- components declarations, procedure declarations begin -- Statements : end architecture_name;

6. Challenging Issues and Solutions 6 • Abstraction of an Entity Declaration: In VHDL, an entity declaration typically defines the input and output ports. Solution: use an input place and an output place to describe the semantics of an input and an output ports, respectively. • Abstraction of an Architecture Body: An architecture body generally specifies the detailed implementation of an entity. Solution: a path is used to describe the semantics of an architecture.

7. Other Issues Related to VHDL Abstraction 7 • Many Other Unique Keywords: Differing from C/C++/ Matlab, VHDL has many other unique keywords, e.g., signal, process, in, out, downto, file, exit, and so on. Solution: For a signal and a process declarations, we use a place and a path to describe the corresponding semantics .

8. A Case Study of VHDL Code for an ADDER 8 • The entity declaration of an ADDER: entity ADDER is port(A: instd_logic_vector(1 downto 0); B: in std_logic_vector(1 downto 0); sum: outstd_logic_vector(2 downto 0) ); end ADDER;

9. Graphic Representation of Entity Declaration 9 Input Ports (A and B): Output Port (sum):

10. Architecture of an ADDER 10 • The architecture body: architecture behv of ADDER is -- define a temporary signal to store the result signal result: std_logic_vector(2 downto 0); begin -- the 3rd bit should be carry result <= ('0'&A)+('0'&B); sum(2 downto 0) <= result(2 downto 0); end behv;

11. Graphic Representation of Architecture 11 The following shows a graphic representation of the entity body:

12. Rehosting of the VHDL-ADDER to C/Matlab 12

13. Next Step 13 • To extend XML representation capabilities to handle other VHDL keywords, such as, group, file, exit, and so on. • To complete the inference engine, e.g., to enable the rehosting from VHDL to C++.

14. Q&A 14