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VLSI DESIGN PRESENTATION

Wasiq M. Khan 17th March,2003. 2. Reconfigurable Computing for Digital Signal Processing. Steady advances in VLSI technology and design tools have extensively expanded the application domain of digital signal processing over the past decade.While application-specific

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VLSI DESIGN PRESENTATION

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    1. Wasiq M. Khan 17th March,2003 1 VLSI DESIGN PRESENTATION DSP IMPLEMENTATION ON RECONFIGURABLE COMPUTING

    2. Wasiq M. Khan 17th March,2003 2 Reconfigurable Computing for Digital Signal Processing Steady advances in VLSI technology and design tools have extensively expanded the application domain of digital signal processing over the past decade.While application-specific integrated circuits (ASICs) and programmable digital signal processors (PDSPs) remain the implementation mechanisms of choice for many DSP applications,increasingly new system implementations based on reconfigurble computing is being considered.

    3. Wasiq M. Khan 17th March,2003 3 DSP Implementation Spectrum

    4. Wasiq M. Khan 17th March,2003 4 DSP Implementation Comparison

    5. Wasiq M. Khan 17th March,2003 5 DSP PROCESSORS Compared to ASIC or FPGA hardware solutions a DSP chip is by far the slowest option. DSPs just draw too much power for portable applications. Power down sides of DSP chips become of too much of a deterrent ,most designers have turned to ASIC hardware solutions.A hard-wired , cell based custom chip.An ASIC solution will be faster , more efficient , and cheaper than its DSP chip alternative.

    6. Wasiq M. Khan 17th March,2003 6 PARALLELISM Many characteristics of FPGA devices,in particular,make them especially attractive for use in digital signal processing systems.The fine-grained parallelism found in these devices is well matched to the high sample rates and distributed computation often required of signal processing applications in areas such as image audio,and speech processing.Given the highly pipelined and parallel nature of many DSP tasks,such as image and speech processing,these implementations have exhibited substantially better performance than standard PDSPs

    7. Wasiq M. Khan 17th March,2003 7 Distributed Single-Chip DSP Interconnection Network

    8. Wasiq M. Khan 17th March,2003 8 Hybrid DSP Architecture The parallel execution of the DSP core and the RL resources can often be expressed as simple extensions of DSP instruction sets.The on-chip DMA controllers which many DSPs already have may prove useful for configuring the RL without burdening the processor with the task.

    9. Wasiq M. Khan 17th March,2003 9 DSP With a Reconfigurable Coprocessor Combination The RR both access to the processor register file and the four on-chip memory ports.This makes the RR a cross between a function unit and a coprocessor.It provides flexibility and reduces the requirement of using memory as the means of communication Between the two data paths,further reducing the memory bandwidth burden and allowing tighter cooperation between the DSP core and the RL

    10. Wasiq M. Khan 17th March,2003 10 The FPGA Based Array Processor for an Inosphereric-Imaging Radar This slide has described an FGPA-based system to process signals for a passive radar.The system uses an FPGA based array processor and a DSP board to compute a cross-ambiguity function and a crosscorrelation on the received data.The system is dynamically reconfogurable.It allows users to modify range,delay and decimation factor.

    11. Wasiq M. Khan 17th March,2003 11 Reconfigurable DSP Processor A Reconfigurable architecture which incorporates a reconfigurable coprocessor into a DSP can have performance benefits for a reasonable increase in chip area.In addition,DSPs have many architectural features which make a combination with reconfiguarble logic feasible and beneficial.Despite the raw clock rate disadvantage of DSPs when compared with general purpose microprocessors,DSPs serve an important role in high-performance,embedded computing;A reconfigure processor on-chip can help DSPs exploit more of the parallelism found in digital signal processing applications,thus improving the processors overall performance

    12. Wasiq M. Khan 17th March,2003 12 Designing Digital Signal Processing with FPGAs Designers creating an FPGA implementation begin with the knowledge that the multipliers they will need are often already fabricated on the chip.Whereas DSP processors typically have only 8 dedicated multipliers at their disposal,a higher end FPGA device such as Alteras Stratix offers up to 224 dedicated multipliers plus additional logic element-based multipliers are needed.

    13. Wasiq M. Khan 17th March,2003 13 Designing Digital Signal Processing with FPGAs Complex digital signal processing applications such as finite impulse response (FIR) filters,modulation-demodulation , and encryption call for larger multiplier requirements.Given the number of multipliers available with an FPGA ,the designers job of defining an architecture for these types of digital signal processing applications tends to be quick and extremely flexible.Higher- end FPGA devices often feature multiple DSP blocks that can provide data throughput of up to 56 GMACS.

    14. Wasiq M. Khan 17th March,2003 14 Digital Signal Processing Architecture A typical digital signal processing architecture includes three structures Datapath- a collection of arithmetic operators such as adders and multipliers Controller- finite state machines (FSMs) that sequence the actions of the datapath. Memory-temporary storage elements used while the algorithm executes.

    15. Wasiq M. Khan 17th March,2003 15 What is the major advantage of FPGA over ASIC Once a system designer has arrived at an architecture that runs the algorithm efficiently , she or he typically turns the job over to a team of hard ware designers.This team,in turn, translates the architecture into a register transfer level description in HDL (VHDL or Verilog).This translation allows hardware designers to consider the design at the appropriate level of abstraction.And it is here that a major advantage of FPGA over ASIC can be found.

    16. Wasiq M. Khan 17th March,2003 16 How FPGA Design Deliver Faster Performance During the Place & Route phase of FPGA design,all logic components are located,wiring connections are made,and a final timing analysis is performed.Place and route software,such as Alteras Quartus II uses the hardware designers timing constraints to create optimal logic mapping and placement.Critical timing paths are optimized first to help achieve timing closure faster and deliver faster performance.

    17. Wasiq M. Khan 17th March,2003 17 Implementing DSP on FPGA FPGA that has been optimized to perform a digital signal processing task,will run anywhere from 10 times to more than 1000 times faster than a single DSP chip.Whereas a DSP processor typically employs serial processing,the parallel capacities inherent FPGA architecture will always give them both a significant edge over DSPs.DSPs just draw too much power for portable applications like Cellular Mobile Communications and Wireless LAN.Texas Instrument doesnt use DSP for WLAN.

    18. Wasiq M. Khan 17th March,2003 18 Implementing DSP on FPGA An increasing number of designers are turning to programmable logic devices,or FPGA , as a way to navigate the software-hardware extremes of DSP or ASIC design solutions.An FPGA thats been enhanced for digital signal processing gives you unlimited customizing options in a chip without all the silicon physical-design work required for an ASIC solution.

    19. Wasiq M. Khan 17th March,2003 19 RISE OF FPGA Key tasks to the rise of FPGA in the signal Processing realm could be assigned to hardware to take advantage of optimum speed , power consumption , and per unit costs,while other tasks are performed by software to speed time to market and ease legacy compatibility.With digital signal processing continuing to be a critical component in the evolution of wireless networks and in multimedia .FPGA will grow in their ability to deliver state-of-art signal processing in a fraction of the time than ASIC.

    20. Wasiq M. Khan 17th March,2003 20 Implementing DSP Designs in Altera?Stratix Devices The most commonly used DSP functions are FIR (Finite Impulse response)filters,IIR(Infinite Impulse response filters,FFT(Fast Fourier Transform),DCT (direct Cosine Transform),Encoder/Decoder and Error Correction/Detection functions.All of these blocks perform intensive arithmetic operations such as add,subtract,multiply,multiply-add or multiply-accumulate.

    21. Wasiq M. Khan 17th March,2003 21 Signal flow graph for an 8-trap Direct Form I FIR filter

    22. Wasiq M. Khan 17th March,2003 22 Simplified View of a Stratix DSP Block

    23. Wasiq M. Khan 17th March,2003 23 VHDL Code Describing Multiply-Accumulate Function

    24. Wasiq M. Khan 17th March,2003 24 Verilog Code Describing Multiply-Add/Subtract Function

    25. Wasiq M. Khan 17th March,2003 25 VHDL Code That Infers Dual-Port RAM

    26. Wasiq M. Khan 17th March,2003 26 Verilog Description that Infers Shift Registers

    27. Wasiq M. Khan 17th March,2003 27 SPEECH PROCESSING To support speech processing,a bus-based multi FPGA board,Tabula Rasa,was Programmed to perform Markov searches of speech phonemes.This system is particularly interesting because it allowed the use of behavioral partitioning and contained a codesign environment for specification,synthesis,simulation, and evaluation design phase.Moreover we can perform Speech Recognition based on Speaker Dependent or Speaker Independent.

    28. Wasiq M. Khan 17th March,2003 28 The Changing World of DSP Applications DSP is often found in human computer interface such as Sound Cards Video Cards Speech Recognition DSL Modems CDMA Receiver Chips Read circuitry of hard drive and CD/DVD storage system

    29. Wasiq M. Khan 17th March,2003 29 The Changing World of DSP Applications Wireless communications and multimedia Cellular Mobile Communications,both GSM and CDMA Wireless LANs General Purpose Processors, such as Intel Pentium, can provide much of the signal processing needed for desk-top applications such as audio and video processing.

    30. Wasiq M. Khan 17th March,2003 30 FUTURE WORK A refinement of the programming methodology for the DSP hybrid processor as well as the many issues of interfacing the RL with the DSP.The intention is to make the programming task resemble more of a software creation problem than a hardware design exercise,a requirement crucial in making the architecture usable by DSP programmers and not just hardware designers. Future work will also quantify the effects of frequent reconfiguration on application performance.

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