1 / 37

FIGURES FOR CHAPTER 15 REDUCTION OF STATE TABLES STATE ASSIGNMENT

This chapter in the book includes: Objectives Study Guide 15.1 Elimination of Redundant States 15.2 Equivalent States 15.3 Determination of State Equivalence Using an Implication Table 15.4 Equivalent Sequential Circuits 15.5 Incompletely Specified State Tables

pamelakim
Download Presentation

FIGURES FOR CHAPTER 15 REDUCTION OF STATE TABLES STATE ASSIGNMENT

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

  1. This chapter in the book includes: Objectives Study Guide 15.1 Elimination of Redundant States 15.2 Equivalent States 15.3 Determination of State Equivalence Using an Implication Table 15.4 Equivalent Sequential Circuits 15.5 Incompletely Specified State Tables 15.6 Derivation of Flip-Flop Input Equations 15.7 Equivalent State Assignments 15.8 Guidelines for State Assignment 15.9 Using a One-Hot State Assignment Problems FIGURES FORCHAPTER 15REDUCTION OF STATE TABLES STATE ASSIGNMENT Click the mouse to move to the next page. Use the ESC key to exit this chapter.

  2. Table 15-1: State Table for Sequence Detector

  3. Table 15-2. State Table for Sequence Detector

  4. Figure 15-1a: Reduced State Table for Sequence Detector

  5. Figure 15-1b: Reduced State Graph for Sequence Detector

  6. Figure 15-2

  7. Table 15-3.

  8. Figure 15-3: Implication Chart for Table 15-3

  9. Figure 15-4: Implication Chart After First Pass

  10. Figure 15-5: Implication Chart After Second Pass

  11. Table 15-4.

  12. Figure 15-6a: Graphs for Equivalent Circuits

  13. Figure 15-6b: Graphs for Equivalent Circuits

  14. Figure 15-7: Implication Tables for Determining Circuit Equivalence

  15. Figure 15-8

  16. Table 15-5. Incompletely Specified State Table

  17. Table 15-6. X

  18. Figure 15-9a: Next-State Maps for Table 15-6

  19. Figure 15-9b: Next-State Maps for Table 15-6

  20. Table 15-7.

  21. Figure 15-10: Next-State Maps for Table 15-7

  22. Figure 15-11: Derivation of S-R Equations for Table 15-7

  23. Table 15-8. State Assignments for 3-Row Tables

  24. Figure 15-12: Equivalent Circuits Obtained by Complementing Qk

  25. Figure 15-13: Equivalent Circuits Obtained by Complementing Qk

  26. Table 15-9. C3 A3 B3

  27. Flip-Flop Input EquationsSection 15.7, p. 489 Assignment “A“Assignment “B"Assignment “C" J1 = XQ'2 J2 = XQ1' K1 = XQ2 K1 = X' K2 = X' J1 = X' J2 = X'Q1 J1 = X'Q2 K2 = X'Q1' K2 = X K1 = X J2= X Z = X'Q1 + XQ2 Z = X'Q2 + XQ1 Z = X'Q1' + XQ2‘ D1= XQ2' D2= XQ1' D1= X' + Q2' D2 = X'(Q1+Q2) D1 = X'(Q2 + Q1) D2 = X + Q1Q2

  28. Table 15-10. Nonequivalent Assignmentsfor 3 and 4 States

  29. Table 15-11. Number of Distinct (Nonequivalent) State Assignments

  30. Figure 15-14b

  31. Figure 15-15a: Next-State Maps for Figure 15-14

  32. Figure 15-15b: Next-State Mapsfor Figure 15-14

  33. Figure 15-16: State Table and Assignments

  34. Table 15-12. Transition table for Figure 15-16(a)

  35. Figure 15-17: Next-State and Output Maps for Table 15-12

  36. Figure 15-18: Partial State Graph

  37. Figure 15-19: Multiplier Control State Graph

More Related