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ELEC-2005 Electronics in High Energy Physics Spring term: Integrated circuits and VLSI technology for physics

CERN Technical Training 2005. ELEC-2005 Electronics in High Energy Physics Spring term: Integrated circuits and VLSI technology for physics. Basic Analog Design Giovanni Anelli 15 March 2005 Part II. Outline – Part II. Noise in analog ICs Matching in analog ICs

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ELEC-2005 Electronics in High Energy Physics Spring term: Integrated circuits and VLSI technology for physics

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  1. CERN Technical Training 2005 ELEC-2005Electronics in High Energy PhysicsSpring term: Integrated circuits and VLSI technology for physics Basic Analog Design Giovanni Anelli 15 March 2005 Part II

  2. Outline – Part II • Noise in analog ICs • Matching in analog ICs • Operational Amplifier design examples • Analog design methodology Giovanni Anelli - CERN

  3. Thermal noise in passive components Thermal noise is caused by the random thermally excited vibration of the charge carriers in a conductor. Power spectral density [ V 2 / Hz ] R R There are no sources of noise in ideal capacitors or inductors. In practice, real components have parasitic resistance that does display thermal noise! Giovanni Anelli - CERN

  4. Noise sources in MOS transistors Channel thermal noise: due to the random thermal motion of the carriers in the channel 1/f noise: due to the random trapping and detrapping of mobile carriers in the traps located at the Si-SiO2 interface and within the gate oxide. Bulk resistance thermal noise: due to the distributed substrate resistance. Gate resistance thermal noise: due to the resistance of the polysilicon gate and of the interconnections. Giovanni Anelli - CERN

  5. Noise in circuits Noisycircuit Noiseless circuit To be independent from the gain of a given system, we use the concept of input-referred noise. This allows comparing easily the noise performance of different circuits (with different gains), and calculating easily the Signal-to-Noise Ratio (SNR). At the input of our linear two-port circuit, we use two noise generator (one noise voltage source and one noise current source) to represent the noise of the system regardless the impedance at the input of the circuit and of the source driving the circuit. Giovanni Anelli - CERN

  6. Input-referred voltage noise The MOS transistor is represented by its small-signal equivalent circuit. We can refer the noise sources inside the MOS transistor to the input, obtaining an input-referred voltage noise. Channel thermal noise Gate resistance thermal noise Bulk resistance thermal noise 1/f noise g ideally varies from 1/2 (w.i.) to 2/3 (s.i.) Ka = 1/f noise parameter, technology dependent Usually, the first two terms are the most important Giovanni Anelli - CERN

  7. N-channel noise spectra W = 2 mm, IDS = 0.5 mA, VDS = 0.8 V, VBS = 0 V Giovanni Anelli - CERN

  8. Noise in a DP + Active CM VDD VDD 2I 2I Giovanni Anelli - CERN

  9. Noise in a DP + Active CM VDD 2I Giovanni Anelli - CERN

  10. Outline – Part II • Noise in analog ICs • Matching in analog ICs • Operational Amplifier design examples • Analog design methodology Giovanni Anelli - CERN

  11. The importance of matching Yield of an N-bit flash Analog-to-Digital converter as a function of the comparator mismatch Giovanni Anelli - CERN

  12. Relative & absolute mismatch D1 L1 D2 L2 Mismatch occurs for all IC components (resistors, capacitors, bipolar and MOS transistors) Absolute mismatch Relative mismatch Giovanni Anelli - CERN

  13. Mismatch in MOS transistors IDS1 IDS2 VGS1 VGS2 Mismatch in physical parameters (Na, m, Tox) and layout dimensions (W, L) gives origin to mismatch in electrical parameters (VT, b and therefore ID) Mismatch in Na, m, Tox + Mismatch in W and L Parameter mismatch I mismatch and V offset Giovanni Anelli - CERN

  14. The golden rule: Bigger is better! Random effects “average out” better if the area is bigger. Therefore, for a given parameter P, we expect something like Giovanni Anelli - CERN

  15. Expected mismatch AVth / tox ~ 1 mV·m / nm From the literature A ~ 1 to 3 %·m Usually in a pair of identical transistors the two most important parameter subject to mismatch are the threshold voltage Vth and the current factor b Mismatch can be treated as another source of noise. As in the noise case, different “mismatch” sources can be grouped into one adding the variances (not the standard deviations) Giovanni Anelli - CERN

  16. Differential pair mismatch 2I INVERSION COEFFICIENT The two transistors have the same drain current I.C. Giovanni Anelli - CERN

  17. Current mirror mismatch I The two transistors have the same gate voltage I.C. INVERSION COEFFICIENT Giovanni Anelli - CERN

  18. Offset of a DP + Active CM VDD 2I RANDOM OFFSET (WORST CASE) SYSTEMATIC OFFSET The difference in the drain voltages of T1 and T2 gives origin a difference in the DC currents in the two branches. “COMMON MODE” OFFSET Due to mismatches in the transistors, a common mode signal at the input gives a non zero output voltage signal. Vin T1 T2 Vout T3 T4 Giovanni Anelli - CERN

  19. Outline – Part II • Noise in analog ICs • Matching in analog ICs • Operational Amplifier design examples • Op Amp application examples • Single-Stage Op Amps • Two-Stage Op Amps • Fully Differential Op Amps • Feedback and frequency compensation • Analog design methodology Giovanni Anelli - CERN

  20. The ideal op amp An op amp is basically a voltage-controlled voltage source Vin + Rout Rin Vout Vin - The op amp is ideal when A0 = Rin = ∞, Rout = 0 Giovanni Anelli - CERN

  21. Op amp application examples NONINVERTING CONFIGURATION INVERTING CONFIGURATION R2 Vin Vout Vin Vout R1 R2 BUFFER R1 Vin Vout = Vin The above equations are valid only if the gain A0 of the op amp is very high! Giovanni Anelli - CERN

  22. Single-stage Op Amp VDD The differential pair + active current mirror scheme we have already seen is a single stage op amp. Several different solutions can be adopted to make a Single-stage amplifier. If high gains are needed, we can use, for example, cascode structures. With single-stage amplifiers it is difficult to obtain at the same time high gain and voltage excursion, especially when other characteristics are also required, such as speed and/or precision. Two-stage configurations in this sense are better, since they decouple the gain and voltage swing requirements. T7 T8 T5 T6 Vout Vb1 Vb1 T4 T3 T2 T1 Vin ISS Giovanni Anelli - CERN

  23. Two-stage Op Amp VDD T6 T7 T8 Vout Vin - T1 T2 Vin + Rb T5 T3 T4 The second stage is very often a CSS, since this allows the maximum voltage swing. The output voltage swing in this case is VDD - |2VDS_SAT| Giovanni Anelli - CERN

  24. Two-stage Op Amp VDD T3 T4 In this case we kept the differential behavior of the first stage, and is the current mirror T7-T8 which does the differential-to-single ended conversion. The output is still a CSS. T5 Vb T6 T2 T1 Vin Vout ISS T7 T8 Giovanni Anelli - CERN

  25. Fully Differential Op Amp VDD T3 T4 T5 Vb1 T6 T2 T1 Vin Vout1 Vout2 ISS T7 T8 Vb2 Giovanni Anelli - CERN

  26. Fully Differential Op Amp VDD To increase the gain, we can again make use, in the first stage, of cascode structures. T8 T7 Vb3 Vb3 T6 T5 Vb2 Vb2 T9 T10 Vb1 Vb1 T4 T3 Vout1 Vout2 T2 T1 Vin T11 T12 Vb4 ISS Vb4 Giovanni Anelli - CERN

  27. Feedback + e Vin A(s) Vout F(s) • A(s) is the open loop transfer function • F(s) is the feedback network transfer function • G(s) is the closed loop transfer function • A(s)F(s) is the loop gain • If the feedback is negative, the loop gain is negative • For |Gloop(s)| >> 1, we have that Giovanni Anelli - CERN

  28. Properties of negative feedback • Negative feedback reduces substantially the gain of a circuit, but it improves several other characteristics: • Gain desensitization: the open loop transfer function is generally dependent on many varying quantities, given by the active components in the circuit. Using a passive feedback network, we can reduce the dependence of the gain variation on the variations of the open loop transfer function. • Reduction of nonlinear distortion • Reduction or increase (depending on the feedback topology) of the input and output impedances by a factor 1-Gloop. • Increase of the bandwidth Giovanni Anelli - CERN

  29. Bode diagrams Many interesting properties of the frequency behavior of a given circuit can be obtained plotting the module and the phase of the Transfer Function as a function of the frequency. These plots are called Bode diagrams. In the general case, a transfer function is given by the ratio between two polynomials. The roots of the numerator polynomial are called zeros, the roots of the denominator polynomials are called poles. For example, in the case of alow-pass filter with RC = 1 ms, the Bode diagrams look like: Giovanni Anelli - CERN

  30. Bandwidth increase with feedback + |G(s)| Vin Vout A0 A(s) - f w w0 w0(1+fA0) GBWP The gain-bandwidth product does not change with feedback! Giovanni Anelli - CERN

  31. Stability Criteria + |fA(s)| GREEN: STABLERED: UNSTABLE Vin Vout A(s) - f w  fA(s) w - 90 Barkhausen’s Criteria - 180 |fA(jw1)| = 1  fA(jw1) = - 180 Giovanni Anelli - CERN

  32. Phase Margin We have seen that to ensure stability |fA(s)| must be smaller than 1 before  fA(s) reaches - 180. But, in fact, to avoid oscillation and ringing, we must have a bit more margin.We define phase margin (PM) the quantity 180 +  fA(w1), where w1 is the gain crossover frequency. It can be shown that, to have a stable system with no ringing (for small signals) we must have PM > 60. If we want to have an amplifier which responds to a large input step without ringing, PM must be even higher. |fA(s)| |fA(s)| w w SMALL PM LARGE PM  fA(s)  fA(s) w w - 180 - 180 Giovanni Anelli - CERN

  33. Frequency Compensation RED: BEFORE COMPENSATIONGREEN: AFTER COMPENSATION Single-pole op-amps would always be stable (the phase does not go below - 90). But a typical op-amp circuit always contains several poles (and zeros!). These op-amps can easily be unstable, and they need therefore to be compensated. This is generally done lowering the frequency of the dominant pole. |fA(s)|  fA(s) - 90 - 180 Giovanni Anelli - CERN

  34. Outline – Part II • Noise in analog ICs • Matching in analog ICs • Operational Amplifier design examples • Analog design methodology Giovanni Anelli - CERN

  35. Analog design methodology Define specifications Extract schematic from layout Choose architecture Layout Versus Schematic (LVS) check Simulate schematic Extracted schematic simulations Simulate schematic varying T, VDD, process parameters BLOCK DONE! In a complex design, this will be repeated for every block of the design hierarchy. Masks layout Design Rules Check (DRC) Giovanni Anelli - CERN

  36. Analog design trade-offs NOISE LINEARITY POWER DISSIPATION GAIN ANALOG DESIGN OCTAGON INPUT/OUTPUT IMPEDANCE SUPPLY VOLTAGE VOLTAGE SWINGS SPEED Giovanni Anelli - CERN

  37. Bibliography Books: B. Razavi, Design of Analog CMOS Integrated Circuits, McGraw-Hill International Edition, 2001. P.R. Gray, P.J. Hurst, S.H. Lewis, R.G. Meyer, Analysis and Design of Analog Integrated Circuits, J. Wiley & Sons, 4th edition, 2001. R. Gregorian, Introduction to CMOS Op-Amps and Comparators, J. Wiley & Sons, 1999. R.L. Geiger, P.E. Allen and N.R. Strader, VLSI Design Techniques for Analog and Digital Circuits, McGraw-Hill International Edition, 1990. D.A. Johns and K. Martin, Analog Integrated Circuit Design, J. Wiley & Sons, 1997. Y. Tsividis, Operation and Modeling of The MOS Transistor, 2nd edition, McGraw-Hill, 1999. K. R. Laker and W. M. C. Sansen, Design of Analog Integrated Circuits and Systems, McGraw-Hill, 1994. C. D. Motchenbacher and J. A. Connelly, Low Noise Electronic System Design, John Wiley and Sons, 1993. A. L. McWhorter, Semiconductor Surface Physics, University Pennsylvania Press, 1956, pp. 207-227. Z.Y. Chang and W.M.C. Sansen, Low-noise wide-band amplifiers in bipolar and CMOS technologies, Kluwer Academic Publishers, 1991. Papers: K. R. Lakshmikumar, R. A. Hadaway and M. A. Copeland, "Characterization and Modeling of Mismatch in MOS Transistors for Precision Analog Design", IEEE Journal of Solid-State Circuits (JSSC), vol. 21, no. 6, December 1986, pp. 1057-1066. Behzad Razavi, “CMOS Technology Characterization for Analog and RF Design", JSSC, vol. 34, no. 3, March 1999, p. 268. M.J.M. Pelgrom et al., “Matching Properties of MOS Transistors”, IEEE JSSC, vol. 24, no. 10, 1989, p. 1433. M.J.M. Pelgrom et al., “A 25-Ms/s 8-bit CMOS A/D Converter for Embedded Application”, IEEE JSSC, vol. 29, no. 8, Aug. 1994 , pp. 879-886. R. W. Gregor, "On the Relationship Between Topography and Transistor Matching in an Analog CMOS Technology", IEEE Transactions on Electron Devices, vol. 39, no. 2, February 1992, pp. 275-282. Giovanni Anelli - CERN

  38. CERN Technical Training 2005 ELEC-2005Electronics in High Energy PhysicsSpring term: Integrated circuits and VLSI technology for physics Basic Analog Design Giovanni Anelli 15 March 2005 Part II

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