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IRAM and ISTORE

IRAM and ISTORE. David Patterson, Katherine Yelick, John Kubiatowicz U.C. Berkeley, EECS http://iram.cs.berkeley.edu/{istore}. IRAM Overview. Low power, high performance processor for multimedia Mixed logic and DRAM On-chip bandwidth, low power Vector processing

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IRAM and ISTORE

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  1. IRAM and ISTORE David Patterson, Katherine Yelick, John Kubiatowicz U.C. Berkeley, EECS http://iram.cs.berkeley.edu/{istore}

  2. IRAM Overview • Low power, high performance processor for multimedia • Mixed logic and DRAM • On-chip bandwidth, low power • Vector processing • Parallelism replace high clock • 200 MHz, 3.2 Gflops, 2 Watts • Simple issue and control logic (power, area) • Push complexity into compiler; well-understood model • Compare to SIMD media extensions (MMX, VIS,…) • Multimedia has fine-grained data parallelism. • Scalable, multi-generation instruction set • Working with application experts (video and speech)

  3. ISTORE Overview • Two kill applications for future • Storage and retrieval • Design points • 2000: 80 nodes in 3 racks • 2001: 1000 nodes with IBM (?) • 2005: 10K nodes in 1 rack (?) • Add IRAM to 1” disk • Key problems are availability, maintainability, and evolutionary growth (AME) of a thousand node servers • Approach • Hardware built for availability: monitor, diagnostics • New class of benchmarks for AME • Reliable systems from unreliable hw/sw components • Introspection: the system watches itself

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