MICROPROCESSORS AND APPLICATIONS

1. MICROPROCESSORS AND APPLICATIONS Mr. DEEPAK P. Associate Professor ECE Department SNGCE DEEPAK.P

2. UNIT 3 DEEPAK.P

3. 20/8/14 DEEPAK.P 8085 BASIC INTERFACING CONCEPTS 3

4. BASIC INTERFACING IN MICROPROCESSOR

5. BASIC INTERFACING IN MICROPROCESSOR • In memory interfacing, 8 bit data line, 16 bit address line , control signals are connected to corresponding lines of memory IC. • In I/O device interfacing, 8 bit data line, only 8 bit address line , control signals are connected to corresponding lines of I/O devices.

6. Classification of I/O Interfacing

7. Data Transfer using I/O STRUCTURE

8. Data Transfer using I/O STRUCTURE • There are three major types of data transfer between the microprocessor and I/O device. • Programmed I/O : In programmed I/O the data transfer is accomplished through an I/O port and controlled by software. • Interrupt driven I/O : In interrupt driven I/O, the I/O device will interrupt the processor, and initiate data transfer. • Direct memory access (DMA) : In DMA, the data transfer between memory and I/O can be performed by bypassing the microprocessor.

9. 27/8/14 DEEPAK.P interfacing I/O devices 9

10. INTERFACING OF INPUT AND OUTPUT DEVICE I/P device Tri state Buffer O/P device D0- D7 Address decoder Logic AD0- AD7 DEEPAK.P

11. INTERFACING OF INPUT AND OUTPUT DEVICE • I/O mapped or programmed interfacing scheme is commonly used. • The data lines are connected to the I/O devices through Tri-state buffer. • Tri- State buffer is enabled from address decoder logic. DEEPAK.P

12. INTERFACING OF INPUT AND OUTPUT DEVICE • The address decoder logic makes an enable signal according to the address data coming from microprocessor. • These address is the address of a ports. • IN and OUT instruction is used for data transfer • Eg. IN ,Port address; IN 02 • OUT, Port address; OUT 03 DEEPAK.P

13. 27/8/14 DEEPAK.P I/O schemes 13

14. Classification of I/O Interfacing DEEPAK.P

15. I/O Addressing Schemes DEEPAK.P

16. I/O Mapped I/O addressing DEEPAK.P

17. I/O Mapped I/O addressing DEEPAK.P

18. INTERFACING OF I&O DEVICE To Data line of µP DEEPAK.P

19. INTERFACING OF I&O DEVICE DEEPAK.P

20. INTERFACING OF I&O DEVICE Darlington Connection DEEPAK.P

21. INTERFACING OF I&O DEVICE DEEPAK.P

22. INTERFACING OF I&O DEVICE DEEPAK.P

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24. INTERFACING OF INPUT DEVICE DEEPAK.P

25. INTERFACING OF INPUT DEVICE DEEPAK.P

26. INTERFACING OF INPUT DEVICE I/P device Tri state Buffer AD0- AD7 D0- D7 O/P device 1 I/O/ M Not Using 1 1 RD Active High DEEPAK.P

27. INTERFACING OF INPUT DEVICE I/P device Tri state Buffer AD0- AD7 D0- D7 O/P device 1 I/O/ M Not Using 0 0 RD Active Low DEEPAK.P

28. INTERFACING OF INPUT DEVICE • The address lines are decoded to generate a signal that is active when the particular port is being accessed. • An IORD signal is generated by combining the IO/M and the RD signals from the microprocessor. DEEPAK.P

29. INTERFACING OF INPUT DEVICE • Lets choose I/O port 0FH for the Input devices. • So, the buffers must be enabled when: • RD = 0IO/M = 1A0-A8= 0FH DEEPAK.P

30. INTERFACING OF INPUT DEVICE A0 A7 DEEPAK.P

31. INTERFACING OF INPUT DEVICE To µP DEEPAK.P

32. INTERFACING OF INPUT DEVICE DIP Switch DEEPAK.P

33. INTERFACING OF INPUT DEVICE Active Low DEEPAK.P

34. INTERFACING OF INPUT DEVICE • Program: • IN 0FH ;input data from port 0F into A • Loop2 CPI Data; Data according to switch position • JNZ Loop1; What to do? • Perform the operation for which when switch is pressed • Loop1 JMP Loop2; Repeat checking of switch condition • HLT DEEPAK.P

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36. INTERFACING OF OUTPUT DEVICE DEEPAK.P

37. INTERFACING OF OUTPUT DEVICE I/P device Tri state Buffer AD0- AD7 D0- D7 O/P device 1 I/O/ M Not Using 1 1 WR Active High DEEPAK.P

38. INTERFACING OF OUTPUT DEVICE • The address lines are decoded to generate a signal that is active when the particular port is being accessed. • An IOWR signal is generated by combining the IO/M and the WR signals from the microprocessor. DEEPAK.P

39. INTERFACING OF OUTPUT DEVICE DEEPAK.P

40. INTERFACING OF OUTPUT DEVICE DEEPAK.P

41. INTERFACING OF OUTPUT DEVICE DEEPAK.P

42. INTERFACING OF OUTPUT DEVICE DEEPAK.P

43. INTERFACING OF OUTPUT DEVICE DEEPAK.P

44. INTERFACING OF OUTPUT DEVICE DEEPAK.P

45. 20/8/14 DEEPAK.P interfacing AS MEMORY MAPPED i/O 45

46. Memory Mapped I/O addressing DEEPAK.P

47. Memory Mapped I/O Interfacing DEEPAK.P

48. Memory Mapped I/O Interfacing • I/O Devices and memory share the same address space. • Each I/O Device is assigned a unique set of addresses. • When the processor places a particular address on the address lines, the device recognizing this address • The processor requests either a read or a write operation, and the requested data is transferred over the data lines. DEEPAK.P

49. Memory Mapped I/O Interfacing • Input and output transfer using memory mapped I/O are not limited to the accumulator. • Same of 8085 instructions can be used for memory mapped I/O ports. • MOV r, m move the connects of input port whose address is available in (H,L) register pair to any internal register. • LDA address load the acc with the content of the input port whose address is available as a second and third byte of the instruction. DEEPAK.P

50. Memory Mapped I/O Interfacing DEEPAK.P