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Digital Image Processor

Digital Image Processor. Senior Design Project – EE97 Tufts University – EECS Department Spring 2002. Designed and Implemented by:. Paul D’Orlando - Computer Engineering ‘02 Weyant Stone - Computer Engineering ‘02 Yuri Grinshteyn - Computer Engineering ‘02.

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Digital Image Processor

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  1. Digital Image Processor Senior Design Project – EE97 Tufts University – EECS Department Spring 2002

  2. Designed and Implemented by: • Paul D’Orlando - Computer Engineering ‘02 • Weyant Stone - Computer Engineering ‘02 • Yuri Grinshteyn - Computer Engineering ‘02

  3. What is the Digital Image Processor? - Hardware component to perform outboard information processing - Memory interfaced with controller device - Ability to display input and output with built-in VGA interface

  4. Four Major Questions 1. Where is the original image stored? 2. What moves and manipulates the image? 3. Where is the modified image stored? 4. How are the two images viewed?

  5. Where is the Original Image Stored? - Read-only memory - Ability to store reasonably large amount of data - Non-volatile - Ease of programmability

  6. What is an EPROM? - Eraseable Programmable Read-Only Memory - Non-volatile memory - Byte-addressable

  7. The Am27C512 - 512K x 8 bit = 64Kbyte capacity - MegaMax downloader compatible - Asynchronous-access capable

  8. What Moves and Manipulates the Image? - Controller logic - Requires easy programmability, fast prototyping, ease of testability - Common availability

  9. Field-Programmable Gate Arrays (FPGA) - Industry standard for rapid prototyping - Programmable CMOS logic - Versatility vs. ASIC

  10. The FLEX 10K20 - 20,000 gates - 189 user I/O pins - 3.3 – 5 volt operating range - ~13K RAM capacity - Built-in component of UP-1 board - Financially sensible

  11. How are FPGAs Programmed? - Existing design (Verilog, VHDL, schematic) downloaded from PC via JTAG pins - Parallel port connection

  12. Altera Max+PLUS II v10.1 - Compatibility with Flex10K20 chip - Support for code design - Familiarity - Financial sensibility

  13. What are VHDL and Verilog? - Hardware description languages - Logic design using software algorithms - Easy specification of complex designs - Final logic is determined by compiler

  14. ENTITY adder IS PORT( a, b :STD_LOGIC_IN, c, s :STD_LOGIC_OUT;) END adder; ARCHITECTURE add OF adder IS s = a XOR b; c = a AND b; END add; module adder(a, b, s, c); input a, b; output s, c; assign {s,c} = a + b; endmodule VHDL vs. Verilog

  15. How to Program the FLEX 10K20 - Creating project file using software - Compiling, creating floorplan, determining pin assignment - Downloading

  16. Altera’s UP-1 Education Board

  17. Features of the UP-1 - Components - Built-in JTAG and VGA interfaces - User I/O enabled - 25.175 Mhz on-board clock

  18. How to Access the FLEX 10K20 Signals

  19. Where is the Modified Image Stored? - SRAM • Static Random Access Memory • Easily rewritable • Addressing scheme similar to chosen EPROM

  20. The UT621024 - 1024K x 8 bit = 128 Kbyte capacity - Byte-addressable - 5 volt operating range - Asynchronous read/write - Common I/O pins - Active low control

  21. How Are the Two Images Viewed? - VGA interface • Video driver loaded as part of FPGA logic • VGA D-Sub port on UP-1 board • Select switch to determine whether contents of ROM or RAM are displayed

  22. What is VGA? - Video Graphics Adapter - PC video output standard - 640 x 480 pixel display - 60 Hz refresh rate - Driven by 5 signals

  23. The VGA Driver - Five output signals • Horizontal and Vertical Sync • Red, Green, Blue - Row and Column Counters - Uses onboard clock - Outputs one pixel per clock cycle

  24. Implementation

  25. The Basic Design

  26. The Internals of the FPGA

  27. DEMO Design in Altera

  28. What Does the Digital Image Processor Do? - EPROM Data • Holds 8 bars of different colors - FPGA Processes • Reads in and manipulates data from AM27C512 • Outputs processed data to UT621024 • Drives VGA output

  29. DEMO -VGA and board operation

  30. Conclusions - Learned Technology, Design Process - Design Goals achieved - Future Research Directions • Processing algorithm • VGA interface • Alternate Storage Media • ASIC Implementation

  31. Special Thanks To… - Professor C. Hwa Chang - Professor Karen Panetta - Professor Stephen Morrison - Professor Soha Hassoun - Warren Gagosian - Paul Olsen - John Bottari - David Scher

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