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Performing Multi-Phased Radar Processing with a Very Deep FPGA Pipeline

Performing Multi-Phased Radar Processing with a Very Deep FPGA Pipeline Jeffrey T. Muehring and John K. Antonio School of Computer Science University of Oklahoma antonio@ou.edu 2000 MAPLD Conference The 3 rd Annual Military and Aerospace Applications of

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Performing Multi-Phased Radar Processing with a Very Deep FPGA Pipeline

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  1. Performing Multi-Phased Radar Processing with a Very Deep FPGA Pipeline Jeffrey T. Muehring and John K. Antonio School of Computer Science University of Oklahoma antonio@ou.edu 2000 MAPLD Conference The 3rd Annual Military and Aerospace Applications of Programmable Devices and Technologies International Conference September 26-28, 2000

  2. Outline • Review of multiprocessor-based solution for Synthetic Aperture Radar (SAR) • Proposed FPGA-based “deep-pipeline” solution for SAR • An initial comparison of multiprocessor-based and • FPGA-based solutions for SAR • A framework for minimizing power consumption of deep pipelines based on signal activity transformations • Summary

  3. Typical Scenario for SAR “Predator”

  4. Footprint Velocity Range Targets Azimuth Footprint of Aerial Side-Looking SAR

  5. Offset Overlapping Beams

  6. Synthetic Beams

  7. Overview of SAR Processing Two Main Phases of Computation for a SAR Processing    Phase 1 Range Processing Phase 2 Azimuth Processing Outputs Input Data Stream    Typical Timing Diagram for Executing SAR on a Multiprocessor System S2 Processor Sets S1 Time

  8. Typical Communication Requirements for SAR on a Multiprocessor System Phase 2 Azimuth Processing (shown distributed across 4 processors) Phase 1 Range Processing (shown distributed across 3 processors) azimuth processor 4 range processor 3 azimuth processor 3 distributed corner turn range processor 2 azimuth processor 2 pulses range processor 1 range samples range samples azimuth processor 1 pulses Reference: T. Einstein, “Realtime Synthetic Aperture Radar Processing on the RACE Multicomputer,” App. Note 203.0, Mercury Computing Sys, 1996.

  9. Typical Processing Flow for SAR on a Multiprocessor System 1 n n n 1 1 Input Data (Pulse Returns)    m Range Processing (r-tap FIR)* 1 n 1 Output Image m 1 Distributed Corner Turn Azimuth Processing (a-tap FIR)* m 1 *Typically performed using FFT-based fast convolution technique

  10. Outline • Review of multiprocessor-based solution for Synthetic Aperture Radar (SAR) • Proposed FPGA-based “deep-pipeline” solution for SAR • An initial comparison of multiprocessor-based and • FPGA-based solutions for SAR • A framework for minimizing power consumption of deep pipelines based on signal activity transformations • Summary

  11. Tracing of Computational Dependencies for a Single Input Range Bin 1 n n n 1 1 Input Data (Pulse Returns)    (assume r = 3) m Range Processing (r-tap FIR) 1 n 1 (m/2)-th pulse return Output Image m 1 (assume a = 5) Distributed Corner Turn Azimuth Processing (a-tap FIR) m 1

  12. Computation of Output Values Associated with Single Input Range Bin using Proposed Deep-Pipe m m m m n n n n 1 1 1 1 1 1 1 1 Input Data (Pulse Returns)    (assume r = 3, a = 5, n = 10) Deep Pipeline (a  r)-tap FIR interspersed with a  (n - r) delay elements 1 n (m/2)-th pulse return Note: each output value is the sum of a  r weighted input values Computation of Output Image Samples: after c cycles after c + 1cycles after c + n cycles after c + (a  n)cycles      

  13. + + + + + Structure of the Deep-Pipeline Example: no. range bins = n = 4 range kernel size = r = 2 azimuth kernel size = a = 3 R1 R2 R4 R5 R6 R7 R9 R3 R8 R0 > > > > > > > > > > a2r1 a2r0 a1r1 a1r0 a0r1 a0r0 input stream output stream no. registers = (an) – (n – r) no. KCMs = (a  r)

  14. Outline • Review of multiprocessor-based solution for Synthetic Aperture Radar (SAR) • Proposed FPGA-based “deep-pipeline” solution for SAR • An initial comparison of multiprocessor-based and • FPGA-based solutions for SAR • A framework for minimizing power consumption of deep pipelines based on signal activity transformations • Summary

  15. Example SAR Scenarios The following sets of application parameters define three SAR scenarios The following radar parameters are assumed for all scenarios

  16. Computational Parameters for Three Scenarios

  17. Comparison of Multiprocessor-based and FPGA-based Approaches for Three Scenarios • The multiprocessor approach requires complex interconnection network plus significant RAM • The FPGA approach only needs simple systolic connections among FPGAs 1 Based on SHARC 21060 DSPs and assumes fast (FFT-based) convolutions

  18. Outline • Review of multiprocessor-based solution for Synthetic Aperture Radar (SAR) • Proposed FPGA-based “deep-pipeline” solution for SAR • An initial comparison of multiprocessor-based and • FPGA-based solutions for SAR • A framework for minimizing power consumption of deep pipelines based on signal activity transformations • Summary

  19. Power Consumption Model W W Deep Pipeline output stream input stream a0 c0 c1 a1 input signal activities c2 a2

  20. Measured and Predicted Power Consumption for FIR Filter on Xilinx 4036 T. Osmulski, et al, “A Probabilistic Power Prediction Tool for the Xilinx 4000-Series FPGA,” Proceedings of The 5th International Workshop on Embedded/Distributed HPC Systems and Applications (EHPC 2000), in Lecture Notes in Computer Science, May 2000, pp.776-783

  21. Using Activity Transformations to Minimize Power Consumption • Some input lines are “hot” (high capacitance) • other input lines are “cold” (low capacitance) • May be possible to apply linear transformation to input data • to appropriately match input line activity vector to capacitance vector a a’ Deep Pipeline Assume Power Model P(a’) -1 output stream input stream T T • Assuming activity vector ais known or estimated, determine transformation T to minimize power consumption of deep pipeline: Min {P(T(a))} T

  22. Summary • An FPGA-based approach was proposed as an alternative to • the “traditional” multiprocessor approach for SAR processing • The proposed FPGA-based approach looks promising • in terms of inherent hardware complexity, but is probably • not practical for implementation with currently available • FPGA parts • The proposed FPGA-based approach is applicable to • other multi-phased embedded radar applications • (e.g., STAP – Space Time Adaptive Processing) • A framework was proposed for minimizing power consumption • for a class of FPGA designs based on input signal activity • transformations

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