Reconfigurable HPC Research at ORNL using Field-Programmable Gate Arrays (FPGAs)

1. Reconfigurable HPC Research at ORNL using Field-Programmable Gate Arrays (FPGAs) Olaf O. StoraasliFuture Technologies GroupComputer Science and Mathematics

2. THE SUPERCOMPUTER COMPANY Explore FPGAs for future ORNL HPC High-performance computing vendors adopting FPGAs Virtex4 FPGA blades to “accelerate mission-critical applications > 100x” Steve Scott, CTO HPCWire 24/3/0606 “After exhaustive analysis, Cray concluded that, although multi-core commodity processors will deliver some improvement, exploiting parallelism through a variety of processor technologies using scalar, vector, multithreading and hardware accelerators(e.g., FPGAs or ClearSpeed co-processors) creates the greatest opportunity for application acceleration.” ORNL potential benefit: Exceed petaflop goal (reduce power) Contents • Background: Why FPGAs? • ORNL experience: FPGA systems/compilers and applications • ORNL partners: Research Lab, , SRC, ,

3. What’s an FPGA? “User-tailored chip” FPGA Logic slice Xilinx Virtex4 FPGA: 25K slices (miniCPUs) • Logic array: user-tailored to application • On-chip RAM, multipliers, and PowerPC CPUs • Mega-gigabit transceivers and digital signaling processing blocks • Supports 100–1000 operations/clock cycle

4. 1000 800 600 400 200 0 Why FPGAs? • Performance—optimal silicon use (maximize parallel ops/cycle) • Rapid growth—gates, speed, I/O • Low power—1/10th CPUs • Flexible—tailor to application FPGA Virtex4 Pentium

5. ORNL FPGA hardware/compilers • SRC-6 (Carte), Digilent (Viva, VHDL), Nallatech (Viva) • Cray XD1 (MitrionC, DSPlogic/Matlab): 6 FPGAs + 144 Opterons • SGI RASC-Altix/Virtex4s (MitrionC) • Bee2: 5 FPGAs and CHiMPS (via Xilinx), DRC (future) Bee2 (via Xilinx) Cray XD1

6. 8 calls in parallel FTTdd STEP FTRNPE 3 functions in parallel COMP1 FTRNDE FTRNVX FTRNEX 2 calls in parallel FFT UV FFT SHTRNS Porting HPC code spectral transform shallow water model to FPGAs HLL developer profiles HLL compiler CHiMPS, Mitrion (FPGA Tools Inside) FPGA speedup Goal Profile Find parallelism: 80% FFTs More GF/$ GF/Watt Model faster

7. Exploring programming options Compiler, simulator, and debugger Gauss matrix solver Viva: Graphical Icons—3-dimensional MitrionC: Text/flow—1-dimensional + Carte/SRC, CHiMPS-VHDL/Xilinx ,

8. Amber speedup on SRC-6 Speedup increase with problem size

9. Speedup projections

10. Summary • ORNL FPGA research: - Increasingly relevent to HPC - FPGA Systems: Cray, SRC, Nallatech, Digilent, SGI, Bee2 - Compilers: Mitrion-C, Carte, Viva, CHiMPS, DSPlogic - Application speedup: Amber, STSWM, BLAST, SW,… - Partners: Xilinx HPC team, UT, Mitrion, Cray • Next: Evaluate application performance, test DRC Acknowledgement: This research is supported by the Office of Science of the U.S. Department of Energy under Contract No. DE-AC05-00OR22725

11. Contact Olaf Storaasli Future Technologies Group Olaf@ornl.gov 11 Storaasli_ReconfigHPC_0611