Performance Space Modeling for Hierarchical Synthesis of Analog Integrated Circuits

2. Performance Space Modeling for Hierarchical Synthesis of Analog Integrated Circuits Georges Gielen, Trent McConaghy, Tom Eeckelaert ESAT-MICAS, Katholieke Universiteit Leuven, Belgium DAC, June 2005, Anaheim

3. Outline • introduction : hierarchical design • performance estimation • design space organization and traversal • conclusions

4. Analog circuit design steps • gain • slew rate • ... I1,I2,I3,... V1,V2,V3... W1,L1,W2,L2,... circuit specs topology selection circuit sizing sizedschematic • basic problems : • many degrees of freedom • many complex trade-offs [Gielen & RutenbarProc IEEE Dec 2000]

5. meet performance constraints : or • minimize objectives, e.g. power consumption Analog circuit optimization • basic flow : Optimization Engine evaluated circuit performance candidate circuit design Evaluation Engine

6. Problem of design complexity • CPU time is prohibitive for large circuits • data converters • phase-locked loops • frontends

7. specs speed resol INL ... Style 1 Style 2 subblock specs block architecture block1 block2 block3 block4 Hierarchical analog design refinement • for more complex analog circuits : • hierarchical decomposition in subblocks, over multiple levels • choose topology at each level • size all blocks at all levels

8. Multi-objective optimization • generates set of Pareto-optimal solutions: • all solutions which cannot beimproved in any objective withoutdegrading any of the other objectives • shows trade-off between differentobjectives • final decision afterwards,no a-priori weighting coefficients • multi-objective genetic algorithms bit error rate power [De Smedt TCAD 2003]

9. Goal • overall goal: analog system-level design • specifically: • getoptimal tradeoffs at system level • so that an informed decisionon specs can be madeand corresponding device sizes can be determined • if that can’t be done: at least meet system-level constraints • two orthogonal subproblems: • how to estimate performance of circuit • with enough speed to enable sizing • yet with enough (near-SPICE) accuracy to be useful • how to search the (giant) design space in a tractable manner • involves the invocation of a hierarchical design methodology • the challenge is how to traverse the nodes in the hierarchy, such that ultimately optimal system-level tradeoffs can be found • “top-down constraint-driven” is just one option…

10. Outline • introduction : hierarchical design • performance estimation • goals • dynamic modeling and subsets • static modeling and subsets • design space organization and traversal • conclusions

11. Performance estimation goals • the performance estimator should: • input a vector of circuit design parameters (e.g. device sizes) • output a vector of performance metrics (e.g. power, …) • for optimization-based design, the ideal performance estimation methodology would… • have low simulation time • yield a model with low prediction error (“near SPICE”) • work on arbitrary nonlinear circuits • have low construction time performance P a.f.o. design variables Xe.g. GBW, slew rate (SRp,SRn) for OTA a.f.o. transistor currents, widths/lengths

12. Performance estimation • accuracy vs. speed tradeoff • what is a good first-order approximation? • what gets added for more detailed approximations? first- order error (%) Detail model simulation time, complexity

13. Performance estimation performance estimation dynamic model static model

14. Performance estimation performance estimation dynamic model static model “flat” SPICE-like simulator

15. Performance estimation performance estimation dynamic model static model “flat” SPICE-like simulator stan-dard high-capacity

16. “Flat” numerical simulation • numerically solves a set of circuit equations extracted from a topology for a given set of conditions • outputs operating point, waveforms for given topology • use further extraction to compute performance value(s) circuit schematic numerical simulation (with embedded device model) perf. value(s) extraction • pros: works for strongly nonlinear circuits and any characteristic very accurate (it’s the standard for accuracy) high-capacity simulators allow feasible simulation of certain types of much larger circuits • cons: simulation time comparatively slow (though sim-in-loop optimization for basic circuits is finally feasible) no symbolic expressions output

17. Performance estimation performance estimation dynamic model static model “flat” SPICE-like simulator behavioral model stan-dard manual gen. high-capacity

18. Performance estimation performance estimation dynamic model static model “flat” SPICE-like simulator behavioral model stan-dard manual gen. auto-gen: MOR, regression high-capacity [Gielen & Phillips CRC 2005]

19. order ~ 1000-10,000 (Non)linear model order reduction • originally : interconnect modeling • now : (non)linear circuit modeling order ~ 10-100

20. √ * x2 + x3 4.8 Template-free model generator • CAFFEINE steps: • first do one or more (time-domain) simulations • then constructively build a model, following any functional form(i.e. not constrained by a template) • using genetic programming algorithm • extra benefit:the feedback to the user enables human-computer “collaborative” behavioral model design • dx/dt = f(x(t), u(t)) • y(t) = Cx(t) + Du(t) evolve both the vector x, and the functions f, C and D [McConaghy & Gielen, ISCAS 2005]

21. Template-free model generator • CAFFEINE steps: • first do one or more (time-domain) simulations • then constructively build a model, following any functional form(i.e. not constrained by a template) • using genetic programming algorithm • extra benefit:the feedback to the user enables human-computer “collaborative” behavioral model design Model creation: interpretable behavioral model generator input and output waveforms numerical simulation(s) interpretable behavioral model interpretable behavioral model Model simulation: model output waveforms simulate model input waveforms

22. result: 1.31% error Experimental results • experiment:model a latch used in an industrial DAC system (strongly nonlinear circuit)

23. Trade-off complexity vs. error

24. Performance estimation performance estimation dynamic model static model equations manual gen.

25. Performance estimation performance estimation dynamic model static model equations manual gen. auto-gen: symbolic analysis, poly / posy, GP [Gielen & Phillips CRC 2005]

26. Symbolic analysis • derives expressions describing circuit performance metrics (e.g. Zout)as a function of circuit parameters, via topology analysis • e.g. ISAAC, SYMBA (K.U.Leuven) survey : [Gielen, CAD of Analog ICs, IEEE Press 2002, pp. 245-261] Model creation: Symbolic Analysis Perf. value Zout = __ Model simulation: Substitute x into model x = [gm1=__,gm2=__, …] • pros: fast model creation, fast model simulation very predictive (has error control), analyzable equations • cons: does not work for strongly nonlinear circuits and characteristics to get very good accuracy, models too complex to be interpretable

27. Templated model (equation) Templated model (equation) “Templated” symbolic modeling typical steps: • first do LOTS of simulations at different circuit parameter values • then build a model according to a functional template e.g. posynomials [Daems et al. DAC 2002] [Daems et al. TCAD 2003] Model creation: Build symbolic model (equation) based on template Repeat for 10,000 designs: Circuit sim data {xi, mi} Numerical simulation Equations, etc Functional template Model simulation: Perf. value Zout = __ Substitute x into model x

28. “Templated” symbolic modeling • pros: • fast model simulation • works for arbitrary nonlinear circuits • somewhat accurate (though very dependent on the training dataand the template) • symbolic expressions are output, aiding understanding • cons: • how do you choose the template?? • accuracy using posynomial templates can be poor • very slow model creation • in many cases, expressions are too big to be interpretable

29. Template-free symbolic modeling typical steps: • first do LOTS of simulations at different circuit parameter values • then build a model, following any functional form(i.e. not constrained by a template) • using genetic programming algorithm [“CAFFEINE”: McConaghy et al. DATE 2005] Model creation: repeat for 10,000 designs: build symbolic model (equation), NO template circuit sim data {xi, mi} numerical simulation template-free model (equation) equations, etc template-free model (equation) Model simulation: perf. value Zout = __ substitute x into model x

30. Template-free symbolic modeling • pros: • fast model simulation • works for arbitrary nonlinear circuits • accurate (though very dependent on training data) • no template to choose (therefore improvements in complexityand accuracy) • symbolic expressions are output, aiding understanding • cons: • very slow model creation due to time to generate simulation samples

31. Template-free symbolic modeling • CAFFEINE-generated symbolic models which have less than 10% training and testing error

32. Template-free symbolic modeling • CAFFEINE-generated models of PM, in order of decreasing error and increasing complexity

33. Performance estimation performance estimation dynamic model static model blackbox regression model equations quadratic, spline, NN, SVM, kriging, etc. manual gen. auto-gen: symbolic analysis, poly / posy, GP

34. blackbox model blackbox model Blackbox regression model typical steps: • first do LOTS of simulations at different circuit parameter values • then build a blackbox model • e.g. train neural network, build support vector machine, fit splines, etc. e.g. [Liu et al. DAC 02], [Wolfe and Vemuri TCAD 03] [Kiely et al. DATE 2004] build blackbox model (e.g. train neural network) repeat for 10,000 designs: Model creation: circuit sim data {xi, mi} numerical simulation equations, etc Model simulation: perf. value Zout = __ substitute x into model x

35. Blackbox regression model • pros: • works for arbitrary nonlinear circuits • fast model simulation • somewhat accurate (though very dependent on the training data!) • cons: • very slow model creation (100’s or 1000’s of simulations) • no symbolic expressions output, therefore less understanding • very hard to find one functional model that fits well everywhere • boosting between multiple models is a possible solution

36. 10 …repeat… …fit a population of individual regressors,then combineto determinefinal prediction Ensemble strategy: boosting • build a sequence of regression models,then combine them • strategy for sequentially resampling/reweighting data, voting = boosting 1 2 …fit another regressionmodel… …fit a regressionmodel… from initialtraining samples… …from predictionerrors in this net,resample, reweighttraining data [Liu, Rutenbar et al. DAC 2002]

37. Another perspective on static modeling aim: interpretable SPICE-accurate models on arbitrary nonlinear circuits Template-Free Symbolic Modeling Numerical Simulation Templated Symbolic Modeling Nonlinear Regression Symbolic Analysis interpretable equations? Spice-acc. on nonlin. circuits?

38. Comparison static modeling approaches each bar is sum of prediction error across six different performance goals (in an application to sizing) [McConaghy & Gielen ISCAS 2005]

39. Outline • introduction : hierarchical design • performance estimation • design space organization and traversal • flat • variants of hierarchical methodologies • comparison • conclusions

40. Design space organisation & traversal design space organization & traversal

41. Design space organisation & traversal design space organization & traversal • pros: • simple in concept and in execution • cons: • does not scale, thus limited to small designs flat

42. Design space organisation & traversal design space organization & traversal top-down constraint-driven flat automatic bottom-up feasibility modeling manual or semi-auto feasibility modeling

43. constraints Subblock 1 subblock 1 designed Subblock 2 subblock 2 designed Subblock n subblock n designed constraints constraints SB 1.1 SB 1.1 designed SB 1.2 SB 1.2 designed SB 1.m SB 1.m designed SB 2.1 designed SB 2.1 Top-down constraint-driven design • map specifications down the hierarchy • meet higher-level specs in some “optimal” way • need power/area estimation and feasibility estimation system designed System Specs

44. subblock 1 designed subblock 2 designed subblock n designed SB 1.1 designed SB 1.2 designed SB 1.m designed SB 2.1 designed Top-down constraint-driven design • bottom-up verification to verify performance against specifications system designed Specs Verify Verify Verify Verify SB 1.1 SB 1.2 SB 1.m SB 2.1

45. Feasibility modeling bottom-up • model feasible performance space of a circuit • for entire range of design parameters in a given process • e.g. [De Bernardinis DAC 2003] [Harjani IJAICSP Jan 1996]

46. Top-down constaint-driven design • pros: • feasible runtime • can provide system-level tradeoffs(assuming good feasibility modeling) • can re-use feasibility models of building blocks • the “natural choice” for advocates of top-down design • cons: • need a way to know what performance combinations ofsub-blocks are feasible • older feasibility modeling approaches were manual and time-consuming, and only met constraints, not improved objectives • but bottom-up feasibility modeling reconciles that • added complexity of a “model” of feasibility • once feasibility modeling is done, still need to do top-down sizing steps (i.e. optimization at each hierarchical node)

47. Design space organisation & traversal design space organization & traversal top-down constraint-driven concurrent flat

48. Concurrent hierarchical methodology • Pros: an alternative to “flat” • Cons: scales badly; more complex than “flat” System Subblock 1 Subblock 2 Subblock n SB 1.1 SB 1.2 SB 1.m SB 2.1 glue constraints optimize all at once via glue constraints

49. FE equalizer : 5 low-noise amps, ~100 passives, 36 program switches, 6 op-modes ~400 devices, flat; ~2-3hrs to SPICE full sizing/biasing ~10hours on 20 CPUs; allspecs met TI Hand CMU1 CMU3 CMU2 Example : equalizer block max noise 25-1104kHz @25oC (nV/Hz1/2) biggest & least noise smaller & less noise area (1000 square grids) [Phelps et al. DAC 2000]

50. Design space organisation & traversal design space organization & traversal bottom-up multi-objective concurrent top-down constraint-driven flat