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Luca Larcher

Modeling Flash Memories for IC Designs. Luca Larcher. Università di Modena e Reggio Emilia Reggio Emilia - Italy luca.larcher@unimore.it. Flash memories. Flash memory market increased exponentially in the last years Flash are pervasive in every modern electronic system.

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Luca Larcher

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  1. Modeling Flash Memories for IC Designs Luca Larcher Università di Modena e Reggio Emilia Reggio Emilia - Italy luca.larcher@unimore.it

  2. Flash memories • Flash memory market increased exponentially in the last years • Flash are pervasive in every modern electronic system

  3. Floating-Gate (FG) transistor • The FG transistor is the basic element of NOR and NAND Flash memories • The information bit is stored by transistor threshold voltage (VT), which can be changed in a non-destructive way by injecting/removing charge to/from FG

  4. Sourcelines Single NOR Flash = FG MOSFET G S D NOR Flash array • In a NOR array, a cell, i.e. a FG transistor is identified by a WL – BL cross Bitlines (BL) Wordlines (WL)

  5. Bitlines BSL 16 Wordlines Select Transistors GSL NAND Flash array • NAND Flash cells are organized in strings • Each string is comprised of 32/64 cells, connected in series • High density, i.e. high capacity is thus achieved

  6. Outline • Motivations • Floating Gate (FG) transistor model: • DC model and FG voltage calculation • Transient model • Program/erase current • Stress Induced Leakage Current, SILC • NOR and NAND Flash Spice-like models • Parameters and extraction procedure • Simulation results • Conclusions

  7. Motivations • Designing NAND and NOR Flash memories requires Spice-like circuit simulations, that need accurate compact models to be effective • Flash memory cells are usually replaced with standard MOS in industry circuit simulations • FG potential is usually calculated through the capacitive coupling coefficient method,i= Ci/CT • Constant capacitive coupling coefficients leads to errors in VFG calculation • Optimum models should be: Spice-like, compact, accurate, usable in DC and transient conditions

  8. The FG transistor DC model CPP= interpoly dielectric capacitance VFG= Floating Gate voltage

  9. VFG calculation • VFG is calculated by solving the charge neutrality equation at the FG node: QMOS + QCPP = QP/E • QCPP= CPP(VFG-VCG) • QP/E = charge injected into the FG during program/erase (constant in DC conditions) • QMOS = f(VFG,VS,VB,VD) is a the charge on the MOS gate, which is a complex function of voltages, calculated by means of the MOS model charge equations

  10. Solution of charge equation • The charge neutrality equation is an implicit equation in VFG: F(VFG) = QMOS(VFG) + QCPP(VFG) – QW/E = 0 • No analytical solution due to the complex QMOS expression • Spice-like simulator solves it numerically through suitable convergence algorithms • F is monotonic versus VFG for all bias combinations (VCG,VS,VB,VD), assuring the uniqueness, i.e. the physical meaning of the derived VFG solution

  11. The FG transistor transient model • Current sources (IW1, IW2, IW3) are included to model program and erase currents, i.e. Fowler-Nordheim (FN) and Channel Hot Electron (CHE) currents

  12. Fowler-Nordheim current sources • Current sources analytically modeling Fowler/Nordheim currents allow reproducing program-erase and erase operations of NAND and NOR Flash memories, respectively. • AT = area of the tunneling region • AFN , BFN = Fowler-Nordheim physical coefficients depending on the Si/SiO2 barrier • FOX= electric field across the tunnel oxide

  13. FOX calculation • VFB = flat-band voltage • S = surface potential drop at Si/SiO2 interface • P = surface potential drop at poly-Si/SiO2 interface • To correctly evaluate S and P, poly depletion and charge quantization effects are taken into account through a self consistent model[1] • The so calculated FOX has been included in the FG model through empirical formulas [1] L. Larcher et al., “A new model of gate capacitance …”, IEEE Trans. Elect. Devices

  14. CHE current source • CHE and Channel Initiated Secondary ELectron (CHISEL) currents can be modeled through simplified approaches allowing modeling the high energy distribution of hot carriers [2] [2] L. Larcher, P.Pavan, “A New Analytical Model of Channel Hot Electron (CHE) and CHannel Initiated Secondary ELectron (CHISEL) …,” MSM 2002, 2002, pp. 738-741.

  15. SiO2 cathode Ep xT anode tox Stress Induced Leakage Current, SILC • SILC[3] is included through current sources allowing simulating the threshold voltage degradation due to the aging of the tunnel oxide induced by P/E cycles • SILC modeled assuming the inelastic Phonon Trap-Assisted Tunneling (PTAT) as conduction mechanism [3] L. Larcher et al., IEEE Trans. Electr. Devices, Vol.48, N.2, 2001, pp.285-288.

  16. NOR Flash model & parameters • The NOR Flash Spice-like model is the FG MOSFET model • Parameters of M1 are extracted applying the standard MOSFET parameter extraction procedure tothe dummy cell, that is a cell with FG and CG short-circuited • Additional parameters from SEM measurements and TCAD simulations : FG-CG capacitance; parameters of current sources • Practically, no additional costs compared to a standard MOSFET

  17. NAND Flash model & parameters • The NAND Flash memory string model is a sub-circuit comprised of equivalent dummy cell MOSFETs, inter-poly capacitances, coupling capacitances, P/E current sources

  18. NAND Flash model & parameters -2 • Coupling capacitances between FGs of adjacent cells, FCF and CFFB,are additional parameters derived from SEM measurements and TCAD simulations • Parameter of the equivalent MOSFET are extracted from a string of dummy cells, paying attention to correctly account for series resistance effects • Again, current sources can be inserted to account for program/erase Fowler-Nordheim currents

  19. DC – NOR Flash: IDS-VCG W=0.25 mm L=0.375 mm

  20. DC – NOR Flash: IDS-VDS

  21. DC – NOR Flash: IDS-VCG W=0.16 mm L=0.3 mm

  22. DC - NAND Flash: IDS-VCG

  23. Erase – NOR Flash: VT - time Erase bias: D float VS=VB=8 V

  24. Erase – NOR Flash: VT - time

  25. 4 Lines: simulations Symbols: measures 3 2 1 VT (V) 0.3 0.5 0.4 0.6 0 TRISE(ms) VCG-ramp 12V -1 VD=VB=0V VS=0V -2 TRISE -3 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 Time (ms) Program – E2PROM Flash: VT No free parameterto improve the fitting quality!!

  26. Program – E2PROM Flash: tunnel current 60 excellent fitting using real VCG ramp!! VCG ramp VD-ramp Nominal 50 40 Real TRISE ITUN (pA) 30 20 10 Lines: simulations Symbols: measures 0 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 Time (ms)

  27. E2PROMFlash: retention simulation NC = number of P/E cycles E2PROM cell left unbiased in retention VT reduction induced by SILC, included by some current sources

  28. Advantages & conclusions • This Flash memory modeling approach has several advantages • The parameter extraction procedure is simple it is similar to the oneof a standard MOSFET and few additional parameters are derived from SEM measurements and TCAD simulations • The simulation time is comparable to MOSFET • VFG calculation procedure does NOT use capacitive coupling coefficients the VFG calculation is much more accurate compared to the usual method considering capacitive coupling coefficients as constants, which introduces errors

  29. Flash coupling coefficients: CG

  30. Advantages & conclusions -2 • NOR and NAND Flash compact models are simply developed as sub-circuit • DC, transient and reliability simulations of single devices and circuits excellently reproduce measurements withoutfree parameters to improve the fitting quality • Easily scalable: scaling rules are taken into account in the MOSFET model itself, and they do not affect the VFG calculation • Easily upgradeable: voltage and current sources can be replaced/modified independently • Can be used for statistical analysis (effects of statistical fluctuation of critical parameters, …)

  31. References • Paolo Pavan, Luca Larcher, Andrea Marmiroli, Floating Gate devices: Operation and Compact Modeling, Kluwer Academic Publishers, 2004, 140 pp., ISBN 1-4020-7731-9 • L. Larcher et al., Bias and W/L Dependence of Capacitive Coupling Coefficients in Floating Gate Memory Cells, IEEE Trans. on Electron Devices, Vol. 48(9), pp. 2081-2089, 2001. • L. Larcher et al., A New Compact DC Model of Floating Gate Memory Cells Without Capacitive Coupling Coefficients, IEEE Trans. on Electron Devices, Vol.49(2), pp. 301-307, 2002. • L. Larcher et al., A complete model of E2PROM memory cells for circuit simulations, IEEE Trans. on CAD, Vol. 22(8), pp. 1072-1079, 2003. • L. Larcher and P. Pavan, Statistical simulations for Flash memory reliability analysis and prediction, IEEE Trans. on Electron Device, Vol. 51(10), pp. 1636-1643, 2004. • Luca Larcher et al., Modeling NAND Flash memories for circuit simulations, IEEE SISPAD, 2007 • L. Larcher et al., Flash memories for SoC: an overview on system constraints and technology issues, (invited paper) IEEE IWSoC2005, 2005.

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