1 / 8

Memory Level General Subgroup CTL Modeling

Memory Level General Subgroup CTL Modeling. Update. May 11, 2007. Confidential. Memory Level General. Members: Mouli (Leader), Jay, Karen, Geir Scope: Define CTL constructs to describe the Memory Level Information excluding Address/data mapping, Redundancy and Memory Access Mechanism

roger
Download Presentation

Memory Level General Subgroup CTL Modeling

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript


  1. Memory Level General SubgroupCTL Modeling Update May 11, 2007 Confidential

  2. Memory Level General • Members: • Mouli (Leader), Jay, Karen, Geir • Scope: • Define CTL constructs to describe the Memory Level Information excluding Address/data mapping, Redundancy and Memory Access Mechanism • Milestone: VTS2007 ( Delayed)

  3. Memory Level GeneralInitial List • Memory Type • SRAM, DRAM, ROM, FLASH, Single Program ROM, CAM • Synchronous, Asynchronous • Memory template Name • Logical Ports–(x)RW, (y)R, (z)W, (m)M(Match ports) • Port synchronicity • Retention Time • Bypass Mode • Memory Timing (can we make it more general that provide all timing information on the memory. May be in the form of a wrapper, would also include ADT….) • Write Mode Operation (Select During Write Through) • Data Input/Out Stages • Flop, Latch, None • Number of stages • Count Ranges for Bank, Row, Column _ Tri State condition

  4. What Memory Attributes are Covered • Memory Functional Architecture • Describe memory functionality for various memory types at the I/O level • Eg., Read/Write/Write-through/Write-back Operations • Memory Test Architecture • Testing the memory core • Describe the data/address/control signals needed to test the memory core • Testing shadow logic • Describe all signals (I/O level) that enable shadow logic test

  5. Memory Functional ArchitectureAttributes • Memory Structure • Memory Functions ( Are these covered by access or Pin function sub groups) • R/W behaviour • Multiport contentions • Write-back, Write through operations Input# Address Lines# Data Lines# Enables (R/W, CEN, ...)# R/W, M ports# ClocksRegistered inputs Memory Type: SRAM/ROM/DRAM/FLASH/CAM Synchronous/AsynchronousPipelined/Non-pipelinedColumn Mux#banks/rows/columnsRetention time Output# Data LinesTristate condition

  6. Memory Test Architecture Attributes • Test Structure • Test Functionality ( covered by other sub groups?) Input# Test Mode signals(Memory BIST, Logic BIST, ATPG)# Bypass Mode signals ( asynch, synchronous) # Test Data, Address, Control signals ( for shadow logic test)# Other Test Modes ( margins, bit-cell variabilities, etc) Memory Core Output#Test result signals( Done, Error, Test Data)

  7. Sample Template for Memory General Attributes STIL 1.0 { CTL 2005; Design 2005; } Variables { IntegerConstant maxdata ; IntegerConstant maxaddr ; IntegerConstant addrmax ; } Signals { */ Address[Range], Data [Range], Controls in; Data [Range] out; Test address [Range], Test Data [Range} out; Test Control [Range] out; */ . . } Environment “ “ { CTL { Memory Properties { /* ( define rows/bank, CM, synch/asynch, R/W port contentions) ; */ } } CTL Mission Mode { Test Mode Normal ; Family (DRAM/SRAM/ CAM/ Flash/ROM): Internal { / * define all the signals * / } CTL BIST_mode { TestMode Internal Test: Internal { / * define all the signals * / } CTL Bypass_mode { TestMode Bypass Internal { / * define all the signals * / }

  8. Schedule & Milestone

More Related