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IEEE 1394

CASI / ELEC 98. IEEE 1394. A high-speed computer I/O serial bus. By Rachad ALAO Ecole Nationale Supérieure des Télécommunications ralao@email.enst.fr. IEEE 1394 Generic Application. Memory. IEEE 1394 Controller. Local Bus. Local Bus. Chipset. IEEE 1394 Cable. CPU. CPU. Memory.

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IEEE 1394

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  1. CASI / ELEC 98 IEEE 1394 A high-speed computer I/O serial bus By Rachad ALAO Ecole Nationale Supérieure des Télécommunications ralao@email.enst.fr

  2. IEEE 1394 Generic Application Memory IEEE 1394 Controller Local Bus Local Bus Chipset IEEE 1394 Cable CPU CPU Memory PCI Bus IEEE 1394 Controller Generic PC Generic Deported App

  3. IEEE 1394 Generic Controller drafts Receive INT Transmit_Granted FIFO_DS Hold FIFO_R/W Link_request TPA FIFO_Add[7..0] Link_DS Host_DS FIFO_Data[31..0] R/W R/W TPB Link Layer Phy Layer Add[7..0] Host_Add[7..0] Link_DS Local Host Bus Adapter * FIFO Controller Link_Data[7..0] Host_Data[31..0] Link_R/W Power Phy_DS Link_Add[2..0] FIFO_DS Phy_Data[7..0] Link_Data[31..0] FIFO_Data[31..0] Clk ( 50 Mhz ) Clk ( 50 Mhz ) Link_On /Reset Clk ( 33 Mhz ) Power_Down /Reset /Reset * Local Bus Adapter Interface is Bus Dependent! No generic interface can be given.

  4. IEEE 1394 Phy Layer drafts Receive Transmit Data Encoder Transmit_Granted Hold Link_request TPA Link_DS Cable Analog Interface Phy State Machine & Internal Regs R/W Add[7..0] TPB Link_Data[7..0] Phy_DS Power Phy_Data[7..0] Clk ( 50 Mhz ) Receive Data Decoder Link_On Power_Down /Reset

  5. IEEE 1394 Link Layer drafts Receive CRC Transmit_Granted Transmitter FIFO_DS Isoch. Manager Hold FIFO_R/W Link_request FIFO_Add[7..0] Link_DS FIFO_Data[31..0] R/W Link State Machine and Registers Add[7..0] Link_DS Phy Interface Link_Data[7..0] Link_R/W Link_Add[2..0] Phy_DS Phy_Data[7..0] Link_Data[31..0] Isoch. Monitor Clk ( 50 Mhz ) Clk ( 50 Mhz ) Receiver Link_On /Reset Power_Down CRC /Reset

  6. IEEE 1394 FIFO Controller drafts INT FIFO Controller &Internal Regs FIFO_DS FIFO_R/W FIFO_Add[7..0] FIFO_Data[31..0] Host_DS R/W Link_DS Host_Add[7..0] Link_R/W General Receive FIFO Host_Data[31..0] Link_Add[2..0] FIFO_DS Link_Data[31..0] Link Layer Interface Host Adapter Interface FIFO_Data[31..0] Asynch. Transmit FIFO Clk ( 50 Mhz ) /Reset Clk ( 33 Mhz ) Isoch. Transmit FIFO /Reset

  7. IEEE 1394 Phy Layer Analog Interface Draft A_out TPA A_in Cable Analog Interface TPB B_out B_in Power +5V Gnd

  8. IEEE 1394 Phy Layer Transmit Encoder Draft A_out T_Data[1..0] B_out Trans_clk Transmit Encoder Data / Status T_Status[3..0]

  9. IEEE 1394 Phy Layer Receiver Decoder Draft A_in R_Data[1..0] B_in Recv_clk Receive Decoder Data / Status A_out B_out R_Status[3..0]

  10. IEEE 1394 Phy Layer State Machine Draft Receive T_Data[1..0] Transmit_Granted T_clk Hold Link_request R_Data[1..0] R_clk Link_DS R/W Phy State Machine & Internal Regs Add[7..0] Data / Status Link_Data[7..0] T_Status[3..0] Phy_DS Phy_Data[7..0] R_Status[3..0] Clk ( 50 Mhz ) Link_On Power_Down /Reset

  11. IEEE 1394 Link Layer Phy Interface Draft Link_DS Transmit_DS Link_R/W Transmit_Data[7..0] Link_Add[7..0] Control_R/W Link_Data[7..0] Control_Add[7..0] Control_Dout_DS Phy_DS Control_Dout[7..0] Phy_Data[7..0] Control_Din_DS Control_Din[7..0] Phy Interface Receive_DS Receive_Data[7..0] Receive Transmit_Granted Transmit_Granted Hold Hold Link_request Link_request Clk ( 50 Mhz ) Clk ( 50 Mhz ) Link_On Link_On Power_Down Power_Down /Reset /Reset

  12. IEEE 1394 Link Transmitter Draft Transmit_packet Transmit_DS Speed_code[1..0] Frame_pos[1..0] Transmit_Data[7..0] Data[31..0] Next_data_quad Transmitter CRC_data_out CRC_generate CRC_data[31..0] CRC_pattern[31..0] CRC_pattern_ready

  13. IEEE 1394 CRC Module Draft CRC_data_in CRC_pattern[31..0] CRC_generate CRC Module CRC_pattern_ready CRC_data[31..0]

  14. IEEE 1394 Link Receiver Draft Receive Receive_DS Data_quad_strobe Data_quad[31..0] Receive_Data[7..0] Physical_ID[15..0] Check_CRC CRC_check_done Receiver CRC_correct CRC_data_out CRC_generate CRC_data[31..0] CRC_pattern[31..0] CRC_pattern_ready

  15. IEEE 1394 Isochronous Manager Draft Cycle_master 50Mhz Clk Isochronious Manager Update Cycle_start_quad[31..0] Cycle_timer_quad[31..0] Send

  16. IEEE 1394 Isochronious Monitor Draft Cycle_timer_quad[31..0] 50Mhz Clk Isochronious Monitor Channel_reserved[63..0] Isoch_bus_req Isoch_bus_grant Isoch_channel[5..0]

  17. IEEE 1394 Link State Machine Draft Transmit_packet Control_R/W Speed_code[1..0] Control_Add[7..0] Frame_pos[1..0] Control_Dout_DS Transmit_data[31..0] Control_Dout[7..0] Transmit_next_data_quad Control_Din_DS Receive Control_Din[7..0] Data_quad_strobe Data_quad[31..0] Transmit_Granted Physical_ID[15..0] Hold Link_request Check_CRC Link State Machine & Register CRC_check_done CRC_correct FIFO_DS FIFO_R/W FIFO_Add[7..0] FIFO_Data[31..0] Link_DS Link_R/W Link_Add[2..0] Link_Data[31..0] Clk ( 50 Mhz ) /Reset

  18. IEEE 1394 Topology vs. SCSI

  19. IEEE 1394 Topology Local Bus i Bridge 1 Bridge 2 Node A Node A port Node B Node B Node C Node C Node D Node D Node E Node F Cable Portion Node E Local Bus 1 Local Bus 2

  20. IEEE 1394 Packet Example

  21. IEEE 1394 Protocol’s Structure

  22. IEEE 1394 Cable’s connection Shielded signal pair A Power pair 6 mm typical Shielded signal pair B

  23. IEEE 1394 Cable’s connection P P A Device 1 A Device 2 B B

  24. IEEE 1394 Data Signal encoding 0 1 1 1 0 1 0 1 Data Strobe Strobe  Data = Clock This data strobe coding double the jitter tolerance, thus allowing higher bandwidth usage

  25. IEEE 1394 Tree Identification ( Step 1 ) Node A Node B Node C parent_notify = Z0 Node D Node E

  26. IEEE 1394 Tree Identification ( Step 2 ) Node A Node B Node C parent_notify = Z0 Node D Node E child_notify = 1Z

  27. IEEE 1394 Tree Identification ( Step 3 ) Node A Node B Node C child_notify = 1Z Node D Node E

  28. IEEE 1394 Tree Identification ( RCP 1 ) Node A Node B Node C parent_notify = Z0 Node D Node E child_notify = 1Z

  29. IEEE 1394 Tree Identification ( RCP 2 ) Node A Node B Node C child_notify = 1Z Node D Node E

  30. IEEE 1394 Fair Arbitration Interval

  31. IEEE 1394 Fair Arbitration

  32. IEEE 1394 Bus Cycle Description Isochronous (  100S ) Asynchronous (  25S )

  33. IEEE 1394 Basic Example 1 Video Camera Node_ID = 1 PC DVD - RAM Root Isochronous Manager Bus Manager Cycle Master Node_ID = 3 Node_ID = 2

  34. IEEE 1394 Basic Example 2 Isochronous Gap Subaction Gap Cycle_Start Ch. i Ch. j Arbitration TX_DATA_END Cycle_Start Ch. i Ch. j Data Packet Acknowledge Gap Cycle_Start Ch. i Ch. j Data Packet Acknowledge Packet

  35. IEEE 1394 Basic Example 3 Isochronous Gap Cycle_Start Arbitration TX_DATA_END Cycle_Start Ch. K Data Packet

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