Main Project : Simple Processor Mini-Project : Vending Machine Memory

1. Main Project : Simple ProcessorMini-Project : Vending MachineMemory By Oluwayomi B. Adamo

2. Simple Processor

3. Design Specification • Memory • Register • Programming Counter • Instruction Register • ALU • Control Unit • Input • Output

4. Memory

5. Memory(VHDL) ENTITY ram IS GENERIC ( bits: INTEGER := 8; -- # of bits per word words: INTEGER := 16); -- # of words in the -- memory PORT ( wr_ena, clk: IN STD_LOGIC; addr: IN INTEGER RANGE 0 TO words-1; data_in: IN STD_LOGIC_VECTOR (bits-1 DOWNTO 0); data_out: OUT STD_LOGIC_VECTOR (bits-1 DOWNTO 0)); END ram; --------------------------------------------------- ARCHITECTURE ram OF ram IS TYPE vector_array IS ARRAY (0 TO words-1) OF STD_LOGIC_VECTOR (bits-1 DOWNTO 0); SIGNAL memory: vector_array; BEGIN PROCESS (clk, wr_ena) BEGIN IF (wr_ena='1') THEN IF (clk'EVENT AND clk='1') THEN memory(addr) <= data_in; END IF;

6. Memory contd. END IF; END PROCESS; data_out <= memory(addr); END ram;

7. Register(VHDL) • entity reg is port( clk, ld, rst : in std_logic; Data: in std_logic_vector( 2 downto 0); Q: out std_logic_vector( 2 downto 0)); • end reg; • architecture behv of reg is • signal Q_tmp: std_logic_vector( 2 downto 0); • begin • process(clk, ld, rst, data) • begin • if (rst = '0' )then • Q_tmp <= (Q_tmp'range => '0'); • elsif (clk='1' and clk'event) then • if (ld = '1' )then • Q_tmp <= Data; • end if; • end if; • end process; • Q <= Q_tmp; • end behv;