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Indium Phosphide Bipolar Integrated Circuits: 40 GHz and beyond

ISSCC 2003 Special Topic Session: Circuits in Emerging Technologies, February 9, San Francisco. Indium Phosphide Bipolar Integrated Circuits: 40 GHz and beyond. Mark Rodwell University of California, Santa Barbara. rodwell@ece.ucsb.edu 805-893-3244, 805-893-3262 fax.

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Indium Phosphide Bipolar Integrated Circuits: 40 GHz and beyond

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  1. ISSCC 2003 Special Topic Session: Circuits in Emerging Technologies, February 9, San Francisco Indium Phosphide Bipolar Integrated Circuits: 40 GHz and beyond Mark Rodwell University of California, Santa Barbara rodwell@ece.ucsb.edu 805-893-3244, 805-893-3262 fax

  2. Applications of InP HBTs Optical Fiber Transceivers 40 Gb/s: InP and SiGe HBT both feasible ICs now available; market has vanished 80 & 160 Gb/s may come in time within feasibility for scaled InP HBT world may not need capacity for some time WDM might be better use of fiber bandwidth mmWave Transmission 65-80 GHz, 120-160 GHz, 220-300 GHz LinksLow atmospheric attenuation (weather permitting).High antenna gains (short wavelengths).10 Gb/s transmission over 500 meters with 20 cm antennas needs 4 mW transmitter power 59-64 GHz LANs: short range, wideband, broadcast Mixed-Signal ICs for Military Radar/Comms direct digital frequency synthesis, ADCs, DACshigh resolution at very high bandwidths sought

  3. Motivation for InP HBTs Parameter InP/InGaAs Si/SiGe benefit (simplified) collector electron velocity 3E7 cm/s 1E7 cm/s lower tc , higher Jbase electron diffusivity 40 cm2/s ~2-4 cm2/s lower tbbase sheet resistivity 500 Ohm 5000 Ohm lower Rbbcomparable breakdown fields Consequences, if comparable scaling & parasitic reduction: ~3:1 higher bandwidth at a given scaling generation~3:1 higher breakdown at a given bandwidth Problem for InP: SiGe has much better scaling & parasitic reduction Technology comparison today:Production SiGe and InP have comparable speedSiGe has much higher integration scalesProduction 1 mm InP: low NRE, fast design cycle for SSI/MSI ICs to ~90 GHz (cost includes design time as well as $/mm2 Present efforts in InP research community Development of low-parasitic, highly-scaled, high-yield fabrication processes

  4. InP HBT fabrication processes today Mesa processes with self-aligned base contacts: Research labs Moderately low yield → 1000 HBTs/IC300 GHz ft, 400 GHz fmax , 7 V BVCEO, 100 GHz clock~ 0.5 mm emitter width Mesa processes with non-self-aligned base contacts: Production in GaAs HBT foundries (cell phone power amps) Somewhat better yield → 3000 HBTs/IC (?)150 GHz ft, 180 GHz fmax , 7 V BVCEO, 70-90 GHz clock 0.8 mm emitter width, 1.0 $/mm2 Exotic research processes for reduced Ccb: 1) transferred-substrate, 2) strongly undercut collector mesatechnology demonstrations, not IC technologies Present research processes in InP community: early development phasescombine InP materials advantages with SiGe-like processesjunction regrowth, dielectric sidewalls, trenches, pedestal implants… …more detail in later slides

  5. Scaling Required transistor design changes required to double transistor bandwidth (C ’s, t ’s, I/C ’s all reduced 2:1) …easily derived by basic geometric calculations

  6. P base N- SiO2 SiO2 N+ subcollector Parasitic Reduction At a given scaling generation, intelligent choice of device geometry reduces extrinsic parasitics wide emitter contact: low resistance narrow emitter junction: scaling (low Rbb/Ae) thick extrinsic base : low resistance thin intrinsic base: low transit time wide base contacts: low resistancenarrow collector junction: low capacitance Much more fully developed in Si…

  7. Optical Transmitters / Receivers are Mixed-Signal ICs MUX/CMU & DMUX/CDR: mostly digital TIA: small-signal LIA: often limiting Small-signal cutoff frequencies (ft , fmax) are ~ predictive of analog speedLimiting and digital speed much more strongly determined by (I/C) ratiosInP HBT has been well-optimized for ft & fmax, less well for digital speed

  8. How do we improve gate delay ?

  9. Why isn't base+collector transit time so important ? Depletion capacitances present over full voltage swing, no large-signal reduction

  10. Scaling Laws, Collector Current Density, Ccb charging time Collector Field Collapse (Kirk Effect) Collector Depletion Layer Collapse Collector capacitance charging time is reduced by thinningthe collector while increasing current

  11. Challenges with Scaling: Collector-base scaling Mesa HBT: collector under base Ohmics. Base Ohmics must be one transfer length → sets minimum size for collector Solution: reduce base contact resistivity → narrower base contacts allowedSolution: decouple base & collector dimensions e.g. buried SiO2 in junction (SiGe) Emitter Ohmic Resistivity: must improve in proportion to square of speed improvements Current Density: self-heating, current-induced dopant migration, dark-line defect formation Loss of breakdownavalanche Vbr never less than collector bandgap (1.12 V for Si, 1.4 V for InP) ….sufficient for logic, insufficient for power Yieldsubmicron InP processes have progressively decreasing yield

  12. Technology Roadmaps for 40 / 80 / 160 Gb/s

  13. M Dahlstrom (UCSB/ONR), Amy Liu (IQE) InP-collector DHBTs: Self-Aligned Mesa Structure 0.7 um base contact width 0.3 um base contact width 200 nm InP collector, 30 nm InGaAs base 8(1019) /cm3 base doping 1 mm base contacts, 0.5 mm x 7.5 mm emitter junction 0.7 mm emitter contact Collector / Emitter Ratio: 2.0 um / 0.5 um, 1.2 um / 0.5 um Vce=1.7 V J=3.7E5 A/cm2 Vbr,ceo=7 V

  14. UCSB/ONR: Miguel Urteaga Submicron InAlAs/InGaAs HBTs: High power gains at very high frequencies transferred-substrate device 6-40, 75-110, 140-220 GHz Gains are high at 220 GHz, but fmax can’t be extrapolated

  15. UCSB/ONR: S. Lee InP-Collector Double Heterojunction Bipolar Transistors fmax = 460 GHz ft = 139 GHz VBR,CEO = 8 V @ JE =5*104 A/cm2 0.5 m x 8 m emitter (mask) 0.4 m x 7.5 m emitter (junction) 1.0 m x 8.75 m collector 3000 Å collector drift region transferred-substrate process

  16. UCSB/ARO: Y. Wei Large-Area (High Current) DHBTs for mm-Wave Power 8-finger device: 1 x 16 mm emitter, 2 x 20 mm collector VBR,CBO> 7V Key challenges with high-current HBTs: - thermal stability (ballasting) - minimal base feed metal parasitic resistance- reliable electromagnetic models of feed networks

  17. UCSB/ONR: Young-Min Kim InP/InGaAs/InP Metamorphic DHBTs on GaAs substrates Comparable performanceto lattice-matched of similar design. Potential for SSI/MSI InP HBTsin cheap GaAs HBT foundry processes.

  18. UCSB/ONR: Miguel Urteaga 174 GHz, 6.3 dB, Single-Transistor Amplifier 0.3 um transferred-substrate HBT

  19. UCSB/ONR: Miguel Urteaga Multi-Stage 140-220 GHz Amplifiers • Three-stage amplifier designs: 12.0 dB gain at 170 GHz 8.5 dB gain at 195 GHz • Cascaded 50 W stages with interstage blocking capacitors Cell Dimensions: 1.6 mm x 0.59 mm 0.3 um transferred-substrate HBT

  20. UCSB/ARO: Y. Wei 75 GHz, 80 mW Power Amplifier 0.4  0.9 mm die, AE = 16 x (1mm x 16 mm) = 256 mm2 transferred-substrate process Bias: Ic=130 mA, Vce=4.5 V 250-500 mW is feasible; UCSB designs are constrained by yield difficulties with large # of fingers

  21. UCSB/ONR: PK Sundararajan 87 GHz HBT static frequency divider InAlAs /InGaAs/InP MESA DHBT 400 Å base, 2000 Å collector, 9 V BVCEO 200 GHz ft, 180 GHz fmax 2.5 x 105 A/cm2 operation

  22. InPhi slides

  23. InPhi slides

  24. OC-768 Linear Components Transimpedance Amplifier 26 dB Limiting Amplifier Vetury, Pullela, Rodwelll Jaganathan & Pullela Transimpedance (dB ohms) (single-ended) curves with, without PIN parasitics 43 Gb/s Frequency (GHz) -7.8 dBm sensitivity @ 10-12 BER (231-1) PRBS Design Challenges: Gain flatness Peaking due to interconnect inductance, gm element phase shift, Ccb variation, photodiode parasitics, single-ended / differential converter.

  25. K. Krishnamurti et al OC-768 Modulator Driver Design Issues: Gain flatness Distributed line losses, current handling & loaded Z0 Complexity of transmission-line layout Associated low-frequency droopEmitter follower negative resistance → peaking Efficacy of bypass capacitances Common-mode traveling-wave instability 30 dB gain, 40 GHz bandwidth, >10 dB S11 & S22 8 ps rise/fall (20-80%) , ~0.9 ps RMS jitter 3 Vpp single ended output, 6 V differential

  26. 4:1 Multiplexer / CMU OC-768 Digital Components 47 Gb/s 1:4 Demultiplexer / CDR (recovered 10 Gb/s data)

  27. Very strong features of SiGe-bipolar transistors High current density 10 mA/mm2 T-shaped polysilicon emitter 0.25 mm junction wide contact low resistance, high yield Thin intrinsic base: low tb Thick extrinsic base: low Rbb Low Ccb collector junction collector pedestal CVD/CMP SiO2 planarization regrown poly extrinsic base High-yield, planar processing high levels of integration LSI and VLSI capabilities SiGe clock rates up to 65 GHzMuch more complex ICs than feasible in InP HBTInP HBT must reach higher integration scales or will cease to compete

  28. Submicron InP HBT Development: Research Planar HBT: Dielectric Sidewall Process Objective: speed extrinsic parasitic reductiondeep submicron scaling Objective: yield planar processeliminate liftoffeliminate undercut etches Target Applications: High speed (>100 GHz) digital& mixed signal. 160 Gb/s optical fiber transmission Similar research efforts Rockwell/GCS/UCSBVitesse. Lucent. TRW. HRL Labs. Double-poly (SiGe-like) HBT

  29. InP HBTs InP has better electron transport than SiGe → faster if comparable-quality fabrication processes are employed. Adaptation of 1-mm GaAs (cell phone) HBT foundry process to InP → Inexpensive, low NRE, low mask cost, fast design cycle Good process for SSI/MSI optical fiber and mm-wave ICs Not good for larger-scale digital / mixed-signal ICs Conventional but more highly scaled InP HBT processes→ millimeter-wave power to 200 GHz, perhaps beyond. Future markets ? Present efforts in InP research community low-parasitic, highly-scaled, high-yield fabrication processes → 3:1 higher bandwidth at a given scaling generation→ 3:1 higher breakdown at a given bandwidth Substantial risk of failure, substantial benefit if successful.

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