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A family of resource-bound process algebras for modeling and analysis of embedded systems

A family of resource-bound process algebras for modeling and analysis of embedded systems. Insup Lee 1 , Oleg Sokolsky 1 , Anna Philippou 2 . 1 SDRL (Systems Design Research Lab) RTG (Real-Time Systems Group) Department of Computer and Information Science University of Pennsylvania

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A family of resource-bound process algebras for modeling and analysis of embedded systems