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Ultra Fine-Grained Run-Time Power Gating of On-Chip Routers for CMPs

Ultra Fine-Grained Run-Time Power Gating of On-Chip Routers for CMPs . Hiroki Matsutani Michihiro Koibuchi Daisuke Ikebuchi Kimiyoshi Usami Hiroshi Nakamura Hideharu Amano. ( Univ Tokyo, Japan) (NII, Japan) (Keio Univ , Japan) (Shibaura IT, Japan) ( Univ Tokyo, Japan)

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Ultra Fine-Grained Run-Time Power Gating of On-Chip Routers for CMPs