1 / 42

Performance directed energy management using BOS technique

Performance directed energy management using BOS technique. Pratap Ramamurthy Ramanathan Palaniappan University of Wisconsin-Madison. Outline. Introduction BOS Mechanisms Policies Results Conclusion. Introduction. Introduction. Energy consumption in mobile devices and laptops

sharne
Download Presentation

Performance directed energy management using BOS technique

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

  1. Performance directed energy management using BOS technique Pratap Ramamurthy Ramanathan Palaniappan University of Wisconsin-Madison

  2. Outline • Introduction • BOS Mechanisms • Policies • Results • Conclusion

  3. Introduction

  4. Introduction • Energy consumption in mobile devices and laptops • Memory could consume 50% more power than processors • Is there hardware support ? • RAMBUS devices provide capability

  5. Problem Statement • How to save power in memory without hurting performance ? • Solution: BOS • Estimating the optimal amount of memory based on paging activity. • Dynamic resizing of memory !

  6. What is BOS ? • BOS – Ballooning in-OS technique • Tracks current memory requirements • Tracks chip access pattern • Powers down memory chips • Minimizes power consumption

  7. BOS Mechanisms • Ballooning in-OS technique • Power Down • Page Migration • Page Reservation • Invisible Buddy • Chip recovery (Power up) • Chip selection • Intercept memory accesses

  8. BOS policies • Power decision • Disk activity, # chips powered on • Epoch • Time interval between two decisions • Chip selection • Access pattern

  9. Inferences • Operating point balances disk accesses and memory power consumption • Cost of thrashing offsets the power saved from a single chip • Most media applications do not need the entire RAM • Least allocated chips are not the least accessed ones

  10. BOS Architecture Wake up Kpower_d Wait an Epoch Get system parameters Decide to Power off/on Do Nothing Recover PowerPages Clear flags & unPin ON OFF Select Chip Loop all pages in chip Update Chip Power Table (CPT) If occupied Migrate If page is free Pin the page If Locked or reserved Wait & Pounce

  11. BOS Mechanisms

  12. Mechanisms • In-OS Ballooning Techniques • Page Migration • Page Reservation • Invisible Buddy • Chip Recovery • Chip Selection • Intercept Memory Accesses • No Actual Power Down

  13. Power down Selected Chip 1010101010 1010100010 1010001010 1010101010 1010100010 1010001010 1010101010 1010100010 1010001010 1010101010 1010100010 1010001010 1010101010 1010100010 1010001010 1010101010 1010100010 1010001010 1010101010 1010100010 1010001010 1010101010 1010100010 1010001010 1010101010 1010100010 1010001010 1010101010 1010100010 1010001010 1010101010 1010100010 1010001010 1010101010 1010100010 1010001010 1010101010 1010100010 1010001010 1010101010 1010100010 1010001010 Under Memory pressure ??? DISK So replace page using LRU… And Migrate!

  14. Page Migration • When to migrate ? • Kinds of pages • File pages • Anonymous pages • Swap cache pages • Free Pages

  15. Page Migration Mechanism • Mechanism • Data Transfer • Reverse map (thanks to Linux Kernel 2.6) • Remap • Dependant data structures • Page Table • Active LRU and Inactive LRU • Page cache • Swap cache • Buffers • Flags

  16. Page MigrationMajor Data Structures Updated while Migrating Processes 1010101010 1010100010 1010001010 1010101010 1010100010 1010001010 1010101010 1010100010 1010001010 Buffers LRU lists 1010101010 1010100010 1010001010 1010101010 1010100010 1010001010 1. Memcopy 2. Remapping using rmap 3. Update buffers 4. Remove from LRU lists

  17. Page Reservation • Ways to Pin pages • Remove from LRU Lists • Reserve Page • Lock Page • Page count

  18. Free Pages • Buddy allocator • List of free pages • Buddy • Order (0-11) • Locality How to deal with already free pages?

  19. Invisibility in Action (Buddy allocator) 2 1 0 Request for a free page of order 0 Request for a page of order 1 (Invisibility in action) Make the ‘power’ pages invisible

  20. Invisible Buddy • Power Bit • Invisibility – divert page allocation • Other methods? • Why not always remove the page completely from the buddy allocator? • Because the free pages are not necessarily in the buddy

  21. Recovery • Page in the buddy • Clear power bit • That’s it ! • Pages that were migrated • Clear Power bit • Add to the buddy • Reverse Recovery • Recover the last pinned page and move backwards

  22. Partial Recovery • Why would you abort a chip? • Locked pages • Reserved pages • IO activity • Easy solution • Abort chip • Better solution • Wait and Pounce

  23. Policies

  24. Policy • Epoch • Time interval between two decisions • Power decision • Disk activity, # chips powered on • Chip select • Access pattern

  25. Chip Selection Mechanism • Chip pattern table • Access history over 32 epochs • Form a number with the bits and Select the minimum ! • How to monitor chip access ? • Referenced bit in h/w • Clear bits • Examine every epoch The least accessed chip is # 6 The least accessed chip is # 7

  26. Results

  27. Results

  28. Chip access pattern

  29. Results

  30. Results

  31. BOS architecture Wake up Kpower_d Wait an Epoch Get system parameters Decide to Power off/on Do Nothing Recover PowerPages Clear PowerBit & unPin ON OFF Select Chip Loop all pages in chip Update Chip Power Table (CPT) If occupied Migrate If page is free Pin the page If Locked or reserved Wait & Pounce

  32. Power down/up decision If ( # disk_access < α ) power_down() elseif ( # disk_access > β ) power_up() elseif (α < # disk_access < β ) take_no_action() α, β – thresholds, α < β

  33. Results

  34. Results • Other workloads

  35. Conclusion

  36. Conclusion • BOS technique is feasible • BOS helps us to vigorously control memory size • Chip allocation and access pattern have no correlation • Several applications do not require the full memory • Threshold based policy gives reasonable performance • An incorrect chip select could increase migration overhead

  37. Summary • BOS philosophy • Implementation of BOS • Mechanism • Page migration • Invisible buddy • Chip recovery • Chip access pattern • Policy • Study of sample workloads • Threshold based policy

  38. Acknowledgements • lxr.linux.no • We would like to thank the following people for their valuable time and for the immensely helpful discussions in the course of this project • Remzi H. Arpaci-Dusseau • Muthian Sivathanu • Vijayan Prabhakaran • Lakshmi Bairavasundaram • Amit Jhawar for resources

  39. ?

  40. References • Huang et.al. “Design and Implementation of Power-Aware Virtual Memory”, USENIX 2003. • Lebeck et.al. “ Power Aware Page Allocation”, ASPLOS 2000. • Li et.al. “Performance directed energy management for main memory and disks”, ASPLOS 2004. • Delaluz et.al. “Scheduler-Based DRAM Energy Management”, DAC 2002.

  41. Related Work • Power Aware Virtual Memory [1] • Per process chip select • Localized per process page allocation • Performance not considered • Execution Time based energy management [ref] • Hardware support for energy management • Various power modes in RAMBUS • Various power modes in disks

  42. Tough nuts to crack • Absolutely no Documentation for Linux 2.6 • memcpy() • Alternate recovery mechanism • Multiple chip select policy • Alternate Allocator mechanism • Removing from LRU

More Related