1 / 31

Subthreshold SRAMs in 40nm techonology p-2010-062

הפקולטה למדעי ההנדסה Faculty of Engineering Sciences. המחלקה להנדסת חשמל ומחשבים. Subthreshold SRAMs in 40nm techonology p-2010-062. Lidor Pergament & Omer Cohen Mr. Adam Teman , Dr . Alexander Fish. Lecture Contents. Introduction SRAM Overview Novel SRAM bitcell

Download Presentation

Subthreshold SRAMs in 40nm techonology p-2010-062

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript


  1. הפקולטה למדעי ההנדסה Faculty of Engineering Sciences המחלקה להנדסת חשמל ומחשבים SubthresholdSRAMs in 40nm techonologyp-2010-062 Lidor Pergament & Omer Cohen Mr. Adam Teman, Dr. Alexander Fish

  2. Lecture Contents • Introduction • SRAM Overview • Novel SRAM bitcell • Test Chip Architecture • Summary

  3. Memory Classification Memory is classified by 4 major categories Volatility, Access Speed, Capacity and Cost Volatile Non Volatile SRAM DRAM REGISTER CACHE FLASH EEPROM HARD DISK

  4. Motivation & Goal • Minimum energy point in digital circuits is achieved at subthreshold voltages (Vdd < Vt). • Low-voltage operation of SRAM memories in the subthreshold region offers substantial power and energy savings at the cost of speed. • This project focuses on the design and implementation of a novel SRAM bitcell for use in the subthreshold region.

  5. Sram overview

  6. Overview

  7. Bistability – Butterfly Curve • Positive feedback creates two stable points “1” and “0”. • Regenerative property ensures a noisy cell converges back to nominal values.

  8. SRAM – Read Access • Bitlines (BL, BL’) are precharged to VDD • Wordline signal (WL) is asserted • One of the bitlines is pulled down toward GND. • Differential signal (BL-BL’) is amplified to accelerate the process. M1 > M5 Constraint!

  9. SRAM – Write Access • Bitlines are precharged to complementary values. • Worldline signal (WL) is asserted. • Q is pulled down to GND while Q’ is driven to VDD. M6 > M4 Constraint!

  10. SRAM – Subthreshold Challenges • In general, ratioed digital circuits are more likely to fail in subthreshold voltages. • 6T Bitcells cannot operate below 600mV – 700mV. • Read SNM problem - degraded read noise margins decrease bitcell stability. • Write fails under 600mV due to the increase of the pMOS drive in sub-threshold.

  11. Novel 9t srambitcell

  12. The Research Work • Numerous novel low-power SRAM memories have been proposed in recent years. • We studied and analyzed many of the important proposals which include : 6T, 7T, 8T, 9T, 10T bitcells, Virtual VDD, Virtual GND, DCVSL, Voltage Boost, Read Buffer, Read Assist, Voltage Boost, and more …….

  13. Brain Storming

  14. Major Achievements • Two innovative SRAM 9T bitcells, named PSRAM and SFSRAM , aimed at eliminating static power consumption and operated in the subthreshold region were fully designed and analyzed. • Three types of 8-kb 40 nm SRAM test chips, nicknamed RAMBO, were designed for operation at 600mV and below. • We are the first academic research team inIsrael to fully design and fabricate a state-of-the-art 40nm CMOS silicon chip.

  15. Chip Design Workflow

  16. Standard 8T – Schematic and Layout Schematic of a standard 8T SRAM bitcell Stick Diagram of a standard 8T SRAM bitcell

  17. Pseudo SRAM (PSRAM) • Pseudo static behavior - A novel bitcell mechanism disposes of both data node charges while holding a logical “1”. • Leakage current is practically eliminated during this low-power standby mode. • Up to 3.75Xless static power consumption than a standard 8T cell at 0.9V.

  18. PSRAM – Write “1” Operation WBL is driven to “1” and WBLB to “0” CLK synchronizes write access Write wordline (enable) is asserted Q is driven to “1” and QB to “0” Q is discharged to during standby

  19. PSRAM – Power Reduction 1.35X

  20. SFSRAM (Supply Feedback SRAM) • Enables subthreshold write with a Virtual-VDD technique – weakening the Supply VDD during write operation. • A new approach for the design of the Virtual-VDD scheme reduces periphery and thus, reduces write power. • Operates at ultra-low voltages, down to 200mV.

  21. Standard 8T – Revisited Schematic of a standard 8T SRAM bitcell Stick Diagram of a standard 8T SRAM bitcell

  22. SFSRAM – Power Reduction

  23. 40nm test chip

  24. Chip Architecture • 8-kb Array • Read-Bitline division • Level Shifters • Row Decoder • Sense-Amps • Precharge Units • Write Drivers • BIST

  25. 40nm Test Chip - Periphery Schematic of Sensing Unit + Up Shifter Schematic of Write Driver Schematic of WL Driver + Down Shifter

  26. Test Chip Top Level Layout 2.90 um 1.40 um 1.40 mm 1.40 mm

  27. Chip Timing Diagrams SRAM access is synchronized by a clock. Bitline Precharge, write driving and digital logic execute during the high phase and read/write take place during the low phase.

  28. summary

  29. Summary • A fully functional 8-kb array was layed out and designed for the 40nm lp TSMC process. • SFSRAM Memory successfully operates at subthreshold voltages - no additional periphery required. • Additional power savings can be achieved in the PSRAM with a majority bit algorithm.

  30. Summary – Continued • PSRAM consumes up to 3.75X less static power than a standard 8T cell. • We Are The first academic research team in Israel to fully design and fabricate a state-of-the-art 40nm chip.

  31. Questions?? Chocolate Chip Digital Chip

More Related