Opportunities and Challenges for Better Than WorstCase Design

Opportunities and Challengesfor Better Than WorstCase Design Todd Austin (presenter) Valeria Bertacco David Blaauw Trevor Mudge University of Michigan razor@eecs.umich.edu

Traditional Worst-Case Design L H Time-to-Market L H Performance Design-Time Verification and Optimization

Better Than Worst-Case Design Online Checker Hardware Run-Time Verification L H L H Time-to-Market Time-to-Market Typical Case Optimization L H L H Performance Performance

Design complexity Billions and billions of transistors lead to untenable designs… Soft errors upsets in logic and memory Cosmic rays, alpha particles, neutrons, etc… Uncertainty in design parameters Process and temperature variation, supply noise… Power/performance demands Bounding performance, area, and battery life Addressing Challengesin the Nanometer Regime

Example BTWC Design:DIVA Checker Online Checker Hardware Performance Correctness • All core function is validated by checker • Simple checker detects and corrects faulty results, restarts core • Checker relaxes burden of correctness on core processor • Tolerates design errors, electrical faults, defects, and failures • Core has burden of accurate prediction, as checker is 15x slower • Core does heavy lifting, removes hazards that slow checker Core Checker speculative instructions in-order with PC, inst, inputs, addr EX/ MEM IF ID REN REG SCHEDULER CHK CT

Another BTWC Design:Razor Logic Online Checker Hardware Main FF Shadow Latch Main FF 5 9 3 9 MEM 4 9 clk clk clk_del • Double-sampling metastability tolerant latches detect timing errors • Second sample is correct-by-design • Microarchitectural support restores state • Timing errors treated like branch mispredictions

Stabilizer FF Razor FF Razor FF Razor FF Razor FF PC Distributed Pipeline Recovery Cycle: 3 2 5 1 0 7 8 9 6 4 inst3 inst4 inst7 inst1 inst8 inst3 inst4 inst2 inst5 inst6 inst2 IF ID EX MEM (read-only) WB (reg/mem) error bubble error bubble error bubble error bubble recover recover recover recover Flush Control flushID flushID flushID flushID • Builds on existing branch prediction framework • Multiple cycle penalty for timing failure • Scalable design as all communication is local

Opportunities for CAD • Key observation: Infrequent faults in the core design are tolerable. • Opportunities: • Focus only on the critical components, no need to verify ad infinitum • Optimize performance/power for the most common scenarios (typical-case optimization)

Razor Opportunity:Typical-Case Energy Reduction reset Ediff = Eref - Esample Pipeline Voltage Control Function Voltage Regulator Esample Vdd Ediff . . . error signals Eref -  • Energy reduction can be realized with a simple proportional control function • Control algorithm implemented in software

Energy/Performance Characteristics Pipeline Throughput Total Energy, Etotal = Eproc + Erecovery Optimal Etotal Energy of Processor Operations, Eproc Energy of Pipeline Recovery, Erecovery Energy of Processor w/o Razor Support 1% Energy IPC 50% Decreasing Supply Voltage

Razor Opportunity:Typical-Case Optimized Adder Kogge-Stone Adder … G15 P15 G14 P14 G13 P13 G12 P12 G11 P11 G10 P10 G9 P9 G8 P8 G7 P7 G6 P6 G5 P5 G4 P4 G3 P3 G2 P2 G1 P1 G0 P0 Cin

Carry Propagations for Random Data Probability Bit Position Carry Distance

Carry Propagations for Typical Data Probability Bit Position Carry Distance

Typical Case Optimized Adder … G15 P15 G14 P14 G13 P13 G12 P12 G11 P11 G10 P10 G9 P9 G8 P8 G7 P7 G6 P6 G5 P5 G4 P4 G3 P3 G2 P2 G1 P1 G0 P0 Cin ripple carry circuit carry-lookahead circuit

Benefits of Typical Case Optimization • Typical-case performance much better than worst case • Especially for typical-case optimized design

Core CAD Requirement:Observability of Circuit-Level Characteristics IF ID EX MEM WB App Output Architectural Simulator Speed and Scope ArchConfig ArchMetrics Inputs, Voltage, Constraints Delay, Power, Switching Module Circuit Models Fidelity and Observability Circuit Simulator CircuitMetrics Tech Models • Circuit-Aware Architectural Simulator efficiently melds circuit simulation with architectural simulation

Additional CAD Opportunities • For synthesis: • Typical-case library characterization (e.g., pdf of delay) • Synthesize design for target performance, power, etc… • TCO-style optimizations possible for macro-modules • For verification: • Full formal verification for checker components • Profile-directed simulation-based verification for core • For testing: • Checker component can facilitate software-based manufacturing test of core components

Conclusions • Better than worst-case design abandons traditional worst-case design constraints • Couples complex designs with checkers • Enables CAD opportunities for typical-case optimization • Requires tool support for observability, synthesis and verification For more information: http://www.eecs.umich.edu/razor First tutorial at DATE, Munich, March 2005

Opportunities and Challenges for Better Than WorstCase Design