Academic training microelectronics nanoelectronics monolithic pixel detectors 12-14 January 2004

1. Academic trainingmicroelectronicsnanoelectronicsmonolithic pixel detectors12-14 January 2004 Pierre Jarron Lecture 2 CERN EP-MIC

2. Nanoelectronics • Microelectronics and HEP instrumentation • Brief history of microelectronics • Evolution of microelectronics in HEP • Microelectronics at LEP • Microelectronics at LHC • Future trends of microelectronics • Trends in microelectronics and nanoelectronics • Is there an end to CMOS • Ultimate CMOS nanoscale technology • Introduction to mesoscopic physics • Quantum confinement, and electronic transport in nanowires • Quantum dots and Single Electron Tunneling (SET) Transistor • Nanoelectronic systems • Monolithic pixel detector • Hybrid pixel detectors at LHC • Monolithic pixel on bulk CMOS • 3D silicon detector • MAPS APS monolithic pixel detector • DEPFET monolithic pixel detector • Thin film on ASIC pixel detector

3. Slides of the lectures In NICE public account: \\cern.ch\dfs\users\j\jarron\Public Acad-Tra_Micro-Nano_P.Jarron_2004_Lecture1.pps With Java applet inverterFab.jar Acad-Tra_Micro-Nano_P.Jarron_2004_Lecture2.pps Acad-Tra_Micro-Nano_P.Jarron_2004_Lecture3.pps

4. Future Trends

5. Accelerated scaling in 2001

6. Shrinking and mixing technologies

7. MOS device is becoming a nano-object Not really planar!

8. The ultimate nanoscale MOS End of CMOS? When? Theoretical prediction Quantum limit Novel nanoscale MOS devices Nanowire MOS device

9. The ultimate MOSFET J. von Neumann Thermodynamical minimum of energy per information bit Will be theoretically reached in 2015 J. Meindl Minimum switching energy/VDD of a Mosfet Not a realistic VDD! minimum theoretical switching voltage inverter Single electron MOSFET size After J. von Neumann, theory of Self reproducing automata 1966, and J. Meindl,IEEE Vol. 35 No 10 October 2000

10. Towards charge quantum limit

11. MOSFET device fundamental limits • Fundamental quantum limits of CMOS • Quantum confinement in a doped channel caused drain current oscillations • Discrete doping center caused Colomb blockade in channel • Limit of the quantum electronic charge approaches • Drain source tunneling < 5nm Colomb BlockadeChannel charge f(Lg) 10 electrons At 15 nm After J. Gauthier LETI

12. Nanoscale MOSFET device • Novel nanoscale device geometry • No high field in drain region to avoid SCE • Undoped channel to avoid coulomb blockade and doping fluctuation • Metal gate to avoid poly depletion and low threshold voltage • Channel conduction is ballistic • Channel on SOI or SON • Double gate • GAA • FINFET Remark There are plenty of ideas of novel nanoscale device but no solution for interconnections After Likharev 2000

13. Suppression of Short Channel Effects Gate Source Drain Source Gate Drain Gate It is difficult to suppress the short channel effect in the traditional planar device structures. Stronger gate control Three-dimensional gate structures Double-gate MOSFETs GAA MOSFETs Double-gate MOSFETs have been fabricated in many research institutions.

14. Variations of Double-Gate MOSFETs Planar Double-Gate Vertical FinFET IBM (2002 SSDM) Agere (2000 IEDM) Hitachi (Delta) UC Berkeley (2001 IEDM) IBM (2002 SSDM) Intel (2002 SSDM) D Gate Gate Gate n S Si Si n Si n Buried Oxide n Si-substrate

15. Ultimate CMOS Device process • Prof. Hiramoto’s Proposal /Tokyo • 10 nm Gate Length Regime • Semi-planar” SOI MOSFETs • Suppression of short channel effect • Finite body effect factor • Quantum effects in narrow channel MOSFET

16. Requirements and issues • Double-gate MOSFETs are good for • Short channel effects, high-drive current • What are other requirements? • Simple fabrication planar process. • FinFET rather than planar double-gate. • Threshold voltage adjustment. Metal gate, Work-function engineering. • Large threshold voltage fluctuations • Adaptive Vth control will be essential • Metal gate and planar DG does not solve the problem • Need for a fourth terminal to control Vth • Substrate bias is the only solution • A device with a finite body effect factor for voltage threshold control

17. Semi-Planar SOI MOSFETs Gate Gate Si Si Si Si Buried Oxide Buried Oxide Si-substrate Si-substrate Triangular Channel “Low” Fin • Simple planar process. • 3D gate structure for SCE suppression. • Sufficient body effect from the backside. • To compensate threshold voltage variations • Utilize quantum ballistic transport

18. Hiramoto’s sub 10nm MOS design Gate Gate Si Si Si Si Buried Oxide Buried Oxide Si-substrate Si-substrate Semi-planar SOI MOSFET solve Short channel effects Device Vt mismatch Body effect factor Profit from: Quantum effects Channel is nanowires in parallel Triangular Channel “Low” Fin

19. SEM Images of a Channel Array Cross-sectional SEM image of an array of triangular channel Channel BOX T. Saito et al, Si Nano WS, 2001.

20. 1.Triangular nanowire channel - SCE gate Si tSOI tSOI n n n n Si Simulation Box Single-gate Double-gate Triangular wire - Covers only two sides of the triangle. - Short channel effect is better than the double-gate. T. Hiramoto, SOI Conference, 2001.

21. 1.Subthreshold Characteristics Triangular wire channel MOSFETs show better sub threshold characteristics than single-gate SOI MOSFETs. T. Hiramoto, SOI Conference, 2001.

22. 2. Body Effect Gate DVth Log Ids Cg CD Ion1 n+ n+ Vbs1 Csub Depletion layer Ioff1 Vbs2 Vth Vbs Ioff2 Vg Vth2 Vdd Vth1 DVth slope Vth0 DVbs Vbs1 > Vbs2 Vbs 0

23. 2.Body effect in double Gate MOS Planar Double Gate Single Gate SOI Ground Plane n n Si n n Si n Si n Box Vbs Large Cg Csub = 0 Small Cg Small Csub Large Csub Good S factor: Very Good Bad SCE: Good Bad Good Zero Fair Good body T. Hiramoto 2002 SSDM

24. 3. Quantum Narrow Channel Effect Quantum transport should be positively utilized

25. Higher Mobility in <100> Direction H. Majima et al. IEDM, 2001.

26. Quantum effects in MOS channel • Channel coupling reduction • Increases the effective gate thickness • Carrier confinement quantization • Ballistic transport • multi-bands channel quantization • Single particle transport phenomena Channel coupling reduction Multi-bands channel quantization D gate S 21020 e/cm3 =0.2 electrons/nm3 !

27. NANOELECTRONICS • What is nanotechnology • Introduction to mesoscopic physics • Energy and space quantization • Colomb blockade • Quantum transport in nanowire • Quantum dot • SET • SET circuits • Carbon nanotubes • Nanoelectronic systems

28. What is nanoelectronics? “There is plenty of room at the bottom” Richard Feynman - 1959 Human scale Nothing in the laws of physics prevented us from arranging atoms the way we want: "...it is something, in principle, that can be done; but in practice, it has not been done because we are too big. • Device and technology based on quantum mechanics • Mesoscopic objects are the size of the Fermi length • Nanotechnology is about rearranging atoms whichever way we want • Molecular nanotechnology or molecular manufacturing There is plenty of room at the bottom

29. Top down and bottom up We are too big, but we have instruments small enough to handle atoms Scanning Tunneling Microscope Atomic force microscope CO man ! Atomic lattice Alternative to planar process still a Dream !

30. Scaling and mesoscopic physics Properties dramatically change between 100nm to 1nm At micron scale classical physics 10nm to 100 nm Mesoscopic physics At nanometer scale Quantum mechanism

31. Mesoscopic device • Macroscopic device • human scale • Microscopic device • classics physics • Mesoscopic device • crossover regime between classic physics and quantum physics • Molecular device • Quantum mechanics Individual electrons unresolved current flows as a fluid. Scaling is applicable Individual electrons observed size of mesoscopic device comparable to the spread of electron. Wavelength nature of electron becomes important. Complete space and energy quantization Mesoscopic devices DNA and 30nm MOSFET SETs Classical mechanics Quantum mechanics nanotubes Quantum dots atoms molecules MOSFET’s

32. Coulomb blockade in 50 nm MOS

33. Electronic transport: quantization, tunneling • From classical to quantum transport • In macroscopic (semi)conductors • Individual electrons are NOT resolved • Fermi gas, current flows like a fluid, uniform charge density: n.e.Vd • Linear scaling: conductivity and geometry determines Ohm Law. • Mesoscopic devices, wires or dots • Electrons are NOT point charge • Tunnel junction quantizes current flows • Conduction in nanowires is not ohmic Tunnel junction

34. Ballistic transport in nanowire Ohm Law’s is obsolete! Free electron motion in propagation direction, Confinement in the 2 other dimensions

35. Quantum ballistic transport Current flows governed by the time dependent Schrodinger equation Only real part of the wave function is shown

36. Quantum wave ?

37. Electron transport in nanowire nanoscale solid-state devices • Electronic transportno scattering • Ballistic one-dimensional wire transverse motion quantized into discrete modes • Longitudinal motion is free, electrons propagate freely • Value of the quantum resistance R0 = h/2e2 divided by the number of occupied transverse modes. • A single mode, the resistance of a perfect wire is rather large: R0= 13 k But… 2-terminal measurement Quantum resistance 4-terminal measurement No resistance! Resistance appears at the at the contact points with the electronic reservoir Ballistic transport in nanowire is resistance free! After Bell Labs 2001

38. Insight in electron wavefunction Classical point charge, Valid for macroscopic size but not at atomic scale Fermi wavelength defines The effective size of the electron Small for conductor Large for semiconductor Why wave interference plays a role is mesoscopic devices? Because phase coherence of electron wavefunction is stable at nanoscopic scale. • Example of electron wave function in a 0.3m quantum dot, Fermi length in the range of the quantum dot size. • QD size should be smaller then average impurity spacing in the material

39. Quantum effects in nano objects Source Dot Drain Source Dot Drain Scattering and space confinement Nanostructure with size comparable to wavefunction Quantum phase coherence of the wavefunction is kept Energy quantization Confinement of motion quantizes energy into discrete states Mesoscopic Devices QD and SET C smaller dot macroscopic: scattering mesoscopic wave interference Tunneling controlled by gate voltage , SET • Coulomb blockade of tunneling • charging energyassociated with isolated • Island causes Coulomb blockade. • Energy cost q2/C. • Discrete energy levels. Ef Fermilevel Open QD, electrons move freely Closed QD,no propagation, barrier>Ef

40. Quantum energy parameterization Charging energy and quantum confinement energy versus thermal energy Quantum confinement energy Fermi level Si

41. Coulomb Blockade of transport R and C Ne Ne+1 Va -e • Isolated nanoscale island: quantum dot • Characterized by a quantum capacitance Ceff • Island stored energy by Ne electrons in island • Addition of extra electron raises energy by Charging energy • Total electron number of on QD/SET • Fluctuates by ONE N ± one electron • SINGLE electron Tunneling • Current flow becomes possible by tunneling

42. Double tunnel junction – QD Va • Satisfy Heisenberg uncertainty and relation thermodynamic limit • Total charge stored on capacitors = Q 1,2= C1,2 V1,2 • Net charge stored on island Q = Q1 – Q2= ne • Capacitance of the island Ceff = C1+C2 • Va does work transferring charge into and out of the island • When charge stored on either capacitor changes by tunneling, additional polarization charge flows into the lead to maintain charge balance equations Energy change after a tunneling event Work Ws, Q is charge transferred by Va

43. Single electron tunneling transistor • What is a single electron tunneling transistor? • Double tunnel junction with an additional gate • Gate generates additional polarization charge QG • For most gate voltages ONE electron number is allowed • Tunneling is blockaded • At other voltages QD is degenerate for q e • Current flow is possible Stability plot for the SET transistor in Vb-Vg plane. The shaded regions are stable regions. Change in free energy after a tunnel event in junctions 1 and 2 Coulomb oscillations in the SET transistor

44. More explanations on SET… • Electrons may only flow by tunneling onto the first unoccupied energy level EN+1. • Electrons will flow one by one if Vb is increased such that E1>EN+1>ER, to change the Fermi level (electrostatics) of the island • Gate voltage Vg produce the same tunneling conditions by lowering island potential well • If EN+1> E1 transport is blockaded Electron transmitted EN+1 e- E1 ER e- EN Source Island gate Reservoir Source Source Reservoir Reservoir Island gate Island gate Electron tunnels onto island Transport is blockaded Electron tunnels again

45. Quantum dots - Artificial atoms A quantum dot (QD) is a nanostructure that can confine the motion of an electron in all three spatial dimensions. This gives rise to a set of discrete and narrow electronic energy levels, similar to those of atomic physics. Essentially, artificial atoms (quantum dots) are small boxes holding a number of electrons that may be varied at will. As in real atoms, the electrons are attracted to a central location. In a natural atom, this central location is a positively charged nucleus; In an artificial atom, electrons are typically trapped in a bowl-like parabolic potential well in which electrons tend to fall in towards the bottom of the bowl. In most cases the nanostructures resemble "pancakes" in which the electrons are restricted to motion in the x-y plane. Thus the appropriate potential is the two-dimensional harmonic oscillator. Simulation of electron wave functions of 3 “pancakes atoms” By solving Schrödinger's equation ____ ____ ____ ____ ____ E = 5 ____ ____ ____ ____ E = 4 ____ ____ ____ E = 3 ____ ____ E = 2 ____ E = 1 |0 0 ½> |0 0 -½> |1 0 ½> For an excellent introduction to the quantum mechanics of the two-dimensional harmonic oscillator see French & Taylor, "An Introduction to Quantum Physics," pp 454 - 463, plus three exercises on page 469.

46. Artificial atoms – periodic table nx ny E n l E 0 0 1 0 0 1 1 0 2 0 +1 2 0 1 2 0 -1 2 1 1 3 0 +2 3 2 0 3 0 -2 3 0 2 3 1 0 3 3 0 4 0 +3 4 0 3 4 0 -3 4 1 2 4 1 +1 4 2 1 4 1 -1 4 Quantum numbers and energies of the first 10 states Schrödinger's equation can be solved for this potential in both Cartesian and circular coordinates, yielding the following expressions (in units of hn ) for the quantized energy levels. E(nx, ny) = nx + ny + 1    where   nx = 0, 1, 2, 3, ...   and   ny = 0, 1, 2, 3, ... E(n, l ) = 2 n + | l | + 1     where   n = 0, 1, 2, ....        and    l = 0, ±1, ±2, ... As in atoms, Pauli exclusion principle determines the number of electrons of the QD system, 20 electrons in the first 4 energy levels. New periodic table can be built with artificial atoms. Quantum corral Quantum states of iron atoms placed on copper After IBM

47. Operation of SET memory

48. Single electron memory integrated with CMOS a 3 X 3 memory array based on nanometer-scale Coulomb blockade (CB) memory devices. Experimental read/write measured om 2x3 cells SET Memory devices that use fewer electrons per bit than current devices Structures use between one and 10 electrons per bit, DRAM devices use half a million e/bit Laterally formed nanowires produce CB oscillation at temperatures around 60K. Lateral single-electron memory (L-SEM) cells containing MTJs formed using a heavily doped 50nm silicon nanowire integrated into the memory node on a split-gate MOSFET. During the write operation, electrons tunnel through the MTJ on the memory node by applying the write word line voltage (VWWL). The stored voltage is read through the current in a split-gate MOSFET, The two gates on either side of the central memory node act as switch transistors to connect the memory node to the data line, -50mV ('0' state) to +50mV ('1' state) the drain current increases from 1nA/µm to 1µA/µm, which is large enough to be detected by CMOS sense amplifiers. Write pulse of around 10ns. These devices have much lower power dissipation than other memory devices, as around 100 000 times fewer electrons are used for each operation. After Cambridge University's Microelectronics Research Centre and Hitachi Cambridge Laboratory

49. SET operating at room temperature K. Matsumoto, M. Ishii, J. Shirakashi, Y. Oka, A. Kurokawa, and S. Ichimura, Applied Physics Letters Ct = ~3.6 x 10-19 F and Cg = ~3.5 x 10-19 F

50. Logic circuits with SET inverter Experimental SET CMOS inverter Circuit operates at cryogenic temperature After Uni Delft 1999. Number of other circuits have been developed. Toshiba IEDM 2001, the 300K first SET logic based on Hybridization of SET technology with CMOS