Micropipeline design in asynchronous circuit

1. Micropipeline design in asynchronous circuit Wilson Kwan M.A.Sc. Candidate Ottawa-Carleton Institute for Electrical & Computer Engineering (OCIECE) Carleton University Ottawa, Canada March 18, 2002

2. Outline • What is micropipeline in asynchronous circuit? • Basic building blocks of the micropipeline. • Difference between two phase signalling and four phase signalling protocol. • Improvement on the micropipeline. - Double edge triggered D-flop flip • Future work of micropipeline.

3. What is micropipeline? • Micropipeline is a basic building block in an asynchronous circuit. Global clock signal is replaced by the local handshaking communication protocol. • Request and acknowledge signals are primarily used to communicate between two stage of pipeline.

4. C Toggle Basic building blocks of the micropipeline • Muller C-elements • Merger XOR • Toggle • Latch (capture-pass latch in conventional two phase micropipeline)

5. Rin Data in Rin C Ain Ain Latch Toggle Data out Rout Rout Aout Aout Basic building blocks of the micropipeline (cont’) • A two-phase latch control circuit with two to four phase converter

6. Data in Ain Rin C Latch Lt Data out Rout Aout Basic building blocks of the micropipeline (cont’) • A four-phase latch control circuit

7. Basic building blocks of the micropipeline (cont’) • Muller C-element: (static C-element) Vdd X Y Z Vss

8. Data Request Acknowledge Data Request Acknowledge Difference between two phase signalling and four phase signalling protocol • Two-phase handshake protocol: • Four-phase handshake protocol:

9. Improvements on the micropipeline design • To increase the performance and energy efficieny of the micropipeline: • Two phase double edge-triggered D flip-flops replace the “Capture-pass” latches

10. Improvements on the micropipeline design- (Double edge triggered D-flop flip) • 2 phase pipeline circuit with double edge-triggered D-FF’s Rin Aout C tA-A’ td Ain Rout Tevent-Q Dout Din D Q

11. Improvements on the micropipeline design- (Double edge triggered D-flop flip) • For this pipeline circuit to function correctly, two time constraints must be met : • Data setup time (tsu): td > Tievent-Q +Tilogic + ti+1su – ti+1R-A’ • Data hold time (th): tiA-A’ + timin cycle time +Tilogic> ti+1h where forward latency = Tevent-Q +Tlogic + tsu backward latency = tR-A’

12. Improvements on the micropipeline design- (Double edge triggered D-flop flip) • Double edge-triggered D-flip-flop:

13. Improvements on the micropipeline design- (Double edge triggered D-flop flip) • Delay, area and energy/cycle comparison:

14. Future work of micropipeline • GasP pipeline : each stage operates at the speed of a three-inverter ring oscillator.

15. References • I.E. Sutherland, “Micropipeline,” Comm. ACM, vol. 32, no.6, pp. 720-738, June 1989. • K.Y. Yun, P.A. Beerel, and J. Arceo, “High Performance Asynchronous Pipeline Circuits,” Proc. Int’l Symp. Advanced Research in Asynchronous Circuit and Systems pp. 17-28, 1996 • Stephen B, Furber and Paul Day, “Four-Phase Micropipeline Latch Control Circuits,” Vol. 4, no.2, June 1996.