1 / 10

Single bit comparator

Single bit comparator. Single bit comparator. gr: a(1) >a(0). A(1). sm: a(1) <a(0). A(0). eq: a(1)=a(0). Truth table. Boolean equation. Gr <= a(1) and (not a(0)) Le <= a. VHDL Code. entity singlebitcomparator is Port ( a : in std_logic_vector(1 downto 0); en: in std_logic;

tadita
Download Presentation

Single bit comparator

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

  1. Single bit comparator Single bit comparator gr: a(1) >a(0) A(1) sm: a(1) <a(0) A(0) eq: a(1)=a(0) DSD,USIT,GGSIPU

  2. Truth table DSD,USIT,GGSIPU

  3. Boolean equation • Gr <= a(1) and (not a(0)) • Le <= a DSD,USIT,GGSIPU

  4. VHDL Code • entity singlebitcomparator is • Port ( a : in std_logic_vector(1 downto 0); en: in std_logic; • gt : out std_logic; • sm : out std_logic; • eq : out std_logic); • end singlebitcomparator; • architecture Behavioral of singlebitcomparator is • begin • process (en,a) • begin • if (a(1)>a(0)) then • gt <= '1'; sm <= '0'; eq <= '0'; • elsif (a(1) < a(0)) then • gt <= '0'; sm <= '1'; eq <= '0'; • else • gt <= '0'; sm <= '0'; eq <= '1'; • end if; • end process; • end Behavioral; DSD,USIT,GGSIPU

  5. Waveform of single bit comparator DSD,USIT,GGSIPU

  6. 4-bit comparator 4-bit comparator 1-bit comp A 1-bit comp B 1-bit comp 1-bit comp DSD,USIT,GGSIPU

  7. Boolean equation for 4-bit comparator • Let A=a3a2a1a0 • Let B=b3b2b1b0 • Intermediate signal : i3,i2,i1 and i0 • AeqB= i3i2i1i0 • AgtB = a3(b3bar)+i3a2(b2bar)+i3i2a1(b1bar)+i3i2i1a0(b0bar) • AltB = Not(AeqB+AgtB) DSD,USIT,GGSIPU

  8. VHDL code of 4-bit comp • entity comp4bit is • Port ( x : in std_logic_vector(3 downto 0); • y : in std_logic_vector(3 downto 0); • en: in std_logic; • greater : out std_logic; • smaller : out std_logic; • equal : out std_logic); • end comp4bit; • architecture Behavioral of comp4bit is • component singlebitcomparator is • Port ( a : in std_logic_vector(1 downto 0); • en: in std_logic; • gt : out std_logic; • sm : out std_logic; • eq : out std_logic); • end component singlebitcomparator; • signal temp : std_logic_vector(10 downto 0); DSD,USIT,GGSIPU

  9. begin • u1: singlebitcomparator port map(a(1)=>x(3),a(0)=>y(3),en=>en,gt=>temp(0),sm=>temp(1),eq=>temp(2)); • u2: singlebitcomparator port map(a(1)=>x(2),a(0)=>y(2),en=>temp(2),gt=>temp(3),sm=>temp(4),eq=>temp(5)); • u3: singlebitcomparator port map(a(1)=>x(1),a(0)=>y(1),en=>temp(5),gt=>temp(6),sm=>temp(7),eq=>temp(8)); • u4: singlebitcomparator port map(a(1)=>x(0),a(0)=>y(0),en=>temp(8),gt=>temp(9),sm=>temp(10),eq=>equal); • greater <= temp(0) or temp(3) or temp(6) or temp(9); • smaller <= temp(1) or temp(4) or temp(7) or temp(10); • end Behavioral; DSD,USIT,GGSIPU

  10. Waveform of 4-bit comparator DSD,USIT,GGSIPU

More Related