System-level Architectur Modeling for Power Aware Computing

1. System-level Architectur Modeling for Power Aware Computing Dexin Li

2. Background • X2000 Avionics system requirement • Digital Elcetronics Power- 10 times decrease • Analog Elcetronics Power - 2 times decrease • Computer performance - 10 to 20 times increase • Design space exploration • power metrics • power optimization at all levels • system level modeling and optimization • Architectural model and behavior model

3. Motivation • Application-driven for system level modeling • Amdal’s law • complicated system behaviors • design space exploration including power metrics • Current techniques make it possible • COTS availability • a lot of state-of-art power management techniques • Clock gating • bus segmentation • ...

4. What is Architectural Modeling For? • Answer questions from behavior model • What are the working modes a bus controller can be working on? • What are the component parameters used for task scheduling? • What are the possible bus topologies for a certain working mode? • ... • Provide a platform for design space exploration • parameterized/synthesizable/simulatable component library • bus model • system interconnect model • power metrics and architectural constraints

5. COTS Component • Components would be used for • architecture composition • component instantiation • component encapsulation • answer higher level questions • parameter used in high level architecture • working modes for behavioral model • Component properties: • parameterized • synthesizalbe • simulatable

6. Bus Model Definition I • Bus-centric architecture • interconnection of different buses • Firewire • PCI • I2C, ... • Multi-tier bus interconnection • Lower power buses • Reconfigurable buses • statically/dynamically optimizable bus topology

7. Bus Model Definition II • Lower power bus techniques • Serialization • Bus encoding • Bus segmentation • Power aware bus techniques • Topology reconfiguration • find optimal topology offline statically • find optimal topology at runtime • statically computation, dynamically selection • Working modes scheduling • need behavioral model support

8. Bus Model Characterization • Bus parameters: speed, width, length • Bus coding methodology • Bus topology • Bus communication modes • Bus arbitration modes • Bus reconfigurability and reconfiguration cost • Fault-tolerant/self-healing property • Power modes and power management property • Bus control type: central vs. distributed • Bus partition/segmentation property

9. System Hierarchy I • Component encapsulation • To be encapsulated • sub-component parameters • sub-component interfaces • sub bus topologies • Encapsulated • new parameters • new bus/component interfaces • new working modes

10. System Hierarchy II • Architecture simulation model • Working at various granularities • Hierarchical model • Input • components • bus model • interconnection information • constraints • Output • event trace • mapping into power numbers

11. Example: X2000 architecture I • CTOS component • Bus controller (Firewire, I2C, PCI, RS422,...) • Microprocessor ( PPC 750, 603e, ...) • Mass Memory (SRAM, DRAM, Flash) • DSP • sensors, camera • Movement driver, pyro driver • RF communication parts • Bus model • Firewire bus model • PCI bus model • I2C bus model

12. Example: X2000 architecture II • System interconnection • multi-tier bus connection (2-tiers or 3-tiers) • reconfigurable bus architecture (firewire bus) • bus-segmentation • bus interconnection (bus bridge) • Simulation model • Firewire bus simulation • reconfiguration process simulation • communication process simulation • arbitration process simulation