Lecture 24: Examples of Multistage Amps

1. Lecture 24:Examples of Multistage Amps Prof. Niknejad

2. Review: Frequency Resp of Multistage Amplifiers • We have a systematic technique to study amplifier performance (derive transfer function, study poles/zeros/Bode pltos). • In most cases, the systematic approach is too cumbersome. • We have a good qualitative understanding of circuit performance (e.g., CS suffers from Miller effect, CD andd CG are wideband stages …) • Open Circuit Time Constants: Analytical technique is capable of estimating only the dominant (lowest) pole …for a restricted class of amplifiers. University of California, Berkeley

3. The Special Case The transfer function can have no zeroes and must have a dominant pole 1 << 2, 3, …, n Factor denominator: University of California, Berkeley

4. Approximating the Transfer Function Multiply out denominator: Since 1 << 2, 3, …, n  University of California, Berkeley

5. How to Find b1? See P. R. Gray and R. G. Meyer, Analysis and Design of Analog Integrated Circuits (EE 140) for derivation Result: b1 is the sum of open-circuit time constantsiwhichcan be found by considering each capacitor Ci in the amplifier separately and finding its Thévenin resistance RTi i = RTi Ci University of California, Berkeley

6. Finding the Thévenin Resistance • Open-circuit all capacitors (i.e.; remove them) • For capacitor Ci, find the resistance RTiacross itsterminals with all independent sources removed(voltages shorted, currents opened) … might needto apply a test voltage and find the current in somecases. Insight for design: the bandwidth of the amplifier willbe limited by the capacitor that contributes the largest i = RTi Ci  not necessarily the largest Ci University of California, Berkeley

7. Complete Amplifier Schematic Goals:gm1 = 1 mS,Rout =10 M University of California, Berkeley

8. Device Sizes M1: select (W/L)1 = 200/2 to meet specified gm1 = 1 mS  find VBIAS = 1.2 V Cascode current supply devices: select VSG = 1.5 V (W/L)4= (W/L)4B= (W/L)3= (W/L)3B = 64/2 M2: select (W/L)2 = 50/2 to meet specified Rout =10 M find VGS2 = 1.4 V Match M2 with diode-connected device M2B. Assuming perfect matching and zero input voltage,what is VOUT? University of California, Berkeley

9. Output (Voltage) Swing Maximum VOUT Minimum VOUT University of California, Berkeley

10. Two-Port Model Find output resistance Rout n = (1/20) V-1, n = (1/50) V-1 at L = 2 m  ron = (100 A / 20 V-1)-1 = 200 k, rop = 500 k University of California, Berkeley

11. Two-Stage Amplifier Topology Direct DC connection: use NMOS then PMOS University of California, Berkeley

12. Current Supply Design Assume that the reference is a “sink” set by a resistor Must mirror the reference current and generate a sink for iSUP 2 University of California, Berkeley

13. Use Basic Current Supplies University of California, Berkeley

14. Complete Amplifier Topology What’s missing? The device dimensions and the bias voltage and reference resistor University of California, Berkeley

15. Multi-Stage Voltage Amplifier University of California, Berkeley

16. Cutting Through the Complexity • Two Approaches: • Eliminate “background” transistors to reduce clutter • 2. Identify the “signal path” between the input and output University of California, Berkeley

17. First Approach: Find I & V Sources University of California, Berkeley

18. What’s Left? Voltage at base ofQ2 is set by totempole University of California, Berkeley

19. Second Approach: Find Signal Path University of California, Berkeley

20. Identifying the Stages First stage (or two stages): CS/CB cascode Second stage (or two stages): CD/CC voltage buffer Why does this make sense for a voltage amplifier? University of California, Berkeley

21. Find Key Two-Port Parameters Output resistance of cascode: University of California, Berkeley

22. Two-Port Parameters (Cont.) University of California, Berkeley

23. Output Resistance and Voltage Gain Source resistance of the CC stage is the output resistanceof the CD stage (small) Open-circuit voltage gain Av (last two stages have nearly unity gain): University of California, Berkeley

24. DC Bias University of California, Berkeley

25. DC Bias (Cont.) Simplifying assumption: Cascode current supply and totem pole: diode connected devices set both source-gate and source-drain voltages select input bias voltage such that ID1 = ID9 devices M1, Q2, M6, and M7 must have same |VDS| orVCE as M9, Q2B, M6B, and M7B (2nd order effect) sometimes called “replica biasing” University of California, Berkeley

26. Output Swing: VOUT,MIN Minimum output voltage: M10, M3 , and Q2 are “suspects” M10 goes into triode when VOUT = 0.5 V M3 goes into triode when VSD3 = 0.5 V  VOUT = 0.5 V – 0.7 V = -0.2 V Q2 goes into saturation when VCE2 = 0.1 V or VBC2 = 0.6 V VOUT = VB2 – VBC2 + VSG3 – VBE4 = 2 V – 0.6 V + 1.5 V – 0.7 V VOUT = 2.2 V University of California, Berkeley

27. Output Swing: VOUT,MAX Maximum output voltage: Q4, M5, and M6 are “suspects” Q4 goes into saturation when VCE4 = 0.1 V  VOUT = 4. 9 V M5 goes triode when VSD5 = 0.5 V  VOUT = 3.8 V M6 goes triode when VSD6 = 0.5 V  VOUT = VS6 – 0.5 V + VSG3 – VBE4 = 3.5 – 0.5 + 1.5 – 0.7 V = 3.8 V University of California, Berkeley