1 / 9

DDU, DCC and FED Crate Status

DDU, DCC and FED Crate Status. J. Gilmore EMU Meeting FNAL Oct. 21, 2005. baseline. Detector Dependent Unit Receive data from DMB, Format data and send to DCC Detect and report errors Built 10 boards, 40 more on the way (36 required in total). C R A T E C O N T R O L L

thai
Download Presentation

DDU, DCC and FED Crate Status

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

  1. DDU, DCC andFED Crate Status J. Gilmore EMU Meeting FNAL Oct. 21, 2005

  2. baseline Detector Dependent Unit Receive data from DMB, Format data and send to DCC Detect and report errors Built 10 boards, 40 more on the way (36 required in total) C R A T E C O N T R O L L E R D C C D D U D D U D D U D D U D D U D D U D C C D D U D D U D D U Data Concentration CardReceive data from DDUs, Merge & send data to DAQ Will build 10 boards (4 required) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 FED Crates (in USC55) All 5 Crates delivered to CERN optional • FED board dimensions are 9U x 220mm deep • EMU will have 4 FED crates (2 for each Endcap) • 9 DDUs plus 1 or 2 DCCs in a FED crate • Each DDU reads out 13 CSCs – 200 sector of Endcap

  3. FMM output port VME FPGA Input FPGA Control FPGA Input FIFOs SLINK GbE FIFO Mezz Board Production DDU • Functions • Merge data from 15 DMBs • Perform error checking and status monitoring (CRC, word count, L1 number, BXN, overflow, link status) • Communicates w/FMM • Large Buffer Capacity • 2.5 MB buffer • Average DDU data volume estimated to be 0.4kB per L1A at LHC (@1034 lumi) • Buffer can hold over 6000 events • TTC signals from DCC • Slow control via VME Optical Fiber Input (15) GbE/SPY To Local DAQ

  4. DDU Data Input Arrangement ME4 ME3 ME2 ME1 DDU Data Inputs • Each DDU reads out a 200 slice of Endcap - 13 CSCs (15 possible w/ME4-2 upgrade) • CSC sectors are rotated between stations to equalize input data rate between DDUs

  5. VME SLINK Output FIFOs Input FIFOs GbE Optional SPY path Input FPGAs TTCrx Control FPGA DDU data SLINK Final DCC Prototype • Data Concentration • Merge data from 10 DDUs • Send merged data to central DAQ via 1 or 2 SLINKs • Has two optional GbE spy data paths • Fast Control • Receive TTC fiber signals using TTCrx, • Fanout L1A, LHC_clock and other TTC signals to DDUs • Has optional FMM interface

  6. J1: Standard VME64x, for slow control J3: Custom for data transmission DDU DCC and for TTC control DDU DCC DDU DDU DCC DDU Custom Backplane for FED Crate 5 Production Backplanes Built • Designed for 10 DDU to 1 DCC or 2 DCCs • Each DCC can send data on 1 or 2 SLINKs • Can accommodate many data concentration ratios: • 9 DDU to 1 SLINK - EMU data on 4 SLINKs • 5 or 4 DDU to 1 SLINK - 8 SLINKs (baseline plan) • 3 or 2 DDU to 1 SLINK - 16 SLINKs (for S-LHC?) • 1 DDU to 1 SLINK - 36 SLINKs (for SS-LHC?)

  7. FED Production Status • DDU Production • Require 36 + 1 boards, total of 50 will be built • 10 built in August 2005, 40 more by December • Includes DDU requirement for TF • Uses same board, but different firmware • DCC Production • Require 4 boards: have 10 PCBs and all parts • Assemble by December • FED Crates, 4 required • 5 crates received at CERN • 5 production backplanes built

  8. New (Final?) EMU Data Format • Data format details on the Web • http://www.physics.ohio-state.edu/~cms/ddu/ • http://www.physics.ohio-state.edu/~cms/dmb/ • http://www.physics.ohio-state.edu/~cms/cfeb/ • https://uimon.cern.ch/twiki/bin/view/CMS/FEDDataFormats • CFEB Format • Additions to word 99 of each time sample • DMB Format • Added DMB CRC word; Header 5 and Trail changed • DDU Format • Added new fields to Header 2, 3 and Trail-1 • Output status, BoE status, Live channels list • CSC Warning, Full and Error list • Reassigned DDU Status bits 22, 28 to 31

  9. Slice: EMU-to-DAQ Testing • Main CMS DAQ tests with EMU were successful • Test of high rate transfer works perfectly • For now, Main DAQ Filter Unit readout limitations • Only few kB/sec through Main DAQ • No capability for Control and Data storage by EMU • Currently the Local DAQ is our best option • Constants, on-line checks, DQM? How much run time? • DDU/DCC/FED Crate Control software • C++ code exists, ready for implementation • DDU monitoring software • dmonitor: scans DDU VME registers & reports errors • 4 CAEN VME Controllers on order • Available soon for software development

More Related