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Selma Conforti (a) Christophe de La Taille (a) Gisèle Martin-Chassard (a) Ian Xiongbo (b)

FCPPL 2012 Microelectronics IHEP Beijing - OMEGA/LAL Orsay collaboration. Selma Conforti (a) Christophe de La Taille (a) Gisèle Martin-Chassard (a) Ian Xiongbo (b) Wei Wei (b) Wang Zheng (b). OMEGA/LAL-IHEP collaboration (2007-2012). Collaboration laid out at Beijing

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Selma Conforti (a) Christophe de La Taille (a) Gisèle Martin-Chassard (a) Ian Xiongbo (b)

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  1. FCPPL 2012 Microelectronics IHEP Beijing - OMEGA/LAL Orsay collaboration Selma Conforti (a) Christophe de La Taille (a) Gisèle Martin-Chassard (a) Ian Xiongbo(b) Wei Wei (b) Wang Zheng (b)

  2. OMEGA/LAL-IHEP collaboration (2007-2012) • Collaboration laid out at Beijing in April 07 around a Pekinese duck • Goal : design common chips for PM readout and sharing measurement results • 2008 : Wei Wei stayed 6 months in Orsay (feb08-aug08) Design of PARISROC1 asic at LAL • 2009 : Yan Xiongbo stayed one year in Orsay (nov08 –oct09) Measurements of PARISROC1 in Orsay Design of PARISROC2 asic at LAL • 2010 : Characterization of PARISROC2 in parallel at LAL and IHEP and design of ARCHGARD1 asic at IHEP (Xiangbo thesis) • 2011 : Design of ARCHGARD2 at IHEP. Begin LHAASO collab. • 2012: study the use of ARCHGARD2/PARISROC2 asics for LHAASO detectors Gisèle Martin-Chassard

  3. OMEGA/LAL-IHEP collaboration • Wei Wei stayed 6 months in Orsay (feb08-aug08) • He joined the PMm2 project • He designed several parts of the ASIC PArISROC1 developed for PMm2 (high speed amplifier, Wilkinson ADC and TDC) • He co-signed the publications and presentations of the ASIC (NNN08 Paris and TIPP09 Tsukuba) • Yan Xiongbo stayed one year in Orsay (nov. 08 –oct.09) He participated to measurements of PARISROC1 in Orsay He designed blocs of the second version: PARISROC2 (new slow shaper and bandgap) • Characterization of PARISROC2 during 2010 in parallel at LAL and IHEP and Yan Xiangbo designs ARCHGARD asic at IHEP for his thesis • 2011 : beginning of the collaboration in LHAASO between IPNO, OMEGA/LAL Orsay and IHEP Beijing Gisèle Martin-Chassard

  4. PMm² general description • PMm2 : a R&D on a triggerless acquisition for next generation neutrino experiments • Goals : replace large PMTs (20-inch) by macro pixel of 16 smallerones (12-inch) with central ASIC (PARISROC) : • - Triggerless front-end electronics with independent channels; • - Charge and time measurement; • - Common High Voltage; • - Only one wire out (DATA + power supply) to the surface DAQ. Front-end electronic closed to the PMTs array underwater Common High Voltage PMm² stands for “Square Meter Photomultiplier” Gisèle Martin-Chassard

  5. PARISROC ASIC requirements - SoC (System on Chip); -Analog F.E. + charge and time digitization; -16PMTsindependent channels; - 1/3 p.e. 100% trigger efficiency; - Charge dynamic range 0 to 300p.e.(at PMT gain 106); - 1 ns time stamping resolution; - Each channel has a variable gain to compensate gain spread for the 16 PMTs with same HV; - Triggerless mode:All the PMTs signals above the threshold (1/3 p.e.) generate a trigger and charge and time are converted in digital data. Gisèle Martin-Chassard

  6. PARISROC 2 general schematic Gisèle Martin-Chassard

  7. PARISROC2 : digital part 4 modules: Acquisition, Conversion, Read Out and Top manager. Acquisition: Analog memory Conversion: Analog charge and time into 10 bits digital value saved in register (RAM) max. conversion time : 26µs Read Out: RAM read out to an external system • Only hit channels are readout • Readout clock : 40 MHz • Max Readout time (16 ch hit) : 25 µs • 51 bits of data / hit channel : • 4 bits : channel number • 25 bits : coarse time (24 bits counter + 1 bit extra) • 11 bits : charge (10bits ADC + 1bit gain used) • 11 bits : fine time (10bits ADC + 1bit ramp used) SELECTIVE READ OUT Gisèle Martin-Chassard

  8. PARISROC2 prototype Sent for fabrication in November 2009 to AMS foundry Received in February 2010 Technology: AMS SiGe 0.35 µm Surface: 17 mm² Package: CQFP160 Gisèle Martin-Chassard

  9. Trigger efficiency Good linearity down to 35 fC= 5 σ noise σ= 7 fC threshold can be set at 1/3 of p.e. Gisèle Martin-Chassard

  10. Auto-gain test (ADC measurements) The whole chain is, now, tested injecting a charge in the input of the channel: the signal is amplified, auto-triggered, held in the SCA cell and converted by the ADC. The charge measurements for different injected charges setting the gain threshold at 60 p.e. Low gain Up to 570 p.e. residuals < 1 UADC → until 60 p.e. Automatic gain selection Good performance of the whole chain. residuals < 1 UADC → until 570 p.e. High gain Up to 60 p.e. Gisèle Martin-Chassard

  11. TDC ramp measurements The TDC ramp has been reconstructed from the time values saved in the analog memory and converted by the ADC (10-bit). The validation of the good ramp is made automatically tested by IPNO team time dynamic range 100 ns Gisèle Martin-Chassard

  12. PMTs measurements (IPN Orsay lab) 8-in PMT (Hamamatsu R5912) Single p.e. noise spectrum. PARISROC 2 ASIC has been tested with 1-inch and 8-inch PMTs. • Charge measurement of PMTs with gain compensation • Ability of PARISROC to sustain the PMTs counting rate (between 4.5 and 6.7 kHz) • Single photoelectron response with 0.3 pe- threshold, 1550 V Charge histograms 1-inch PMT at a voltage of 1200 V (gain around 107) versus thresholds (350, 385, 390 and 395). The pedestal is at 58 ADC channels. Gisèle Martin-Chassard

  13. PMm2 demonstrator at IPNO 2m x 2m array PARISROC2 chip Watertight box Demonstrator realized by the IPNO with 16 x 8-inch Hamamatsu tubes. Gisèle Martin-Chassard

  14. PMm2 Global Architecture Surface Controller DAQ JAVA Software FPGA Micro-Controller Gisèle Martin-Chassard Submarine cable 100m 16 DATA + Power Clock Ethernet ULB LAPP 10 Bars WATER PRESSURE LAPP 16 PMTs 2m*2m Underwater Front-end Board Front-end ASIC FPGA Common HV IPNO IPNO + LAL Global synoptic of PMm2

  15. Process :Chartered 0.35um Power supply：3.3V 5 channels 1 channel with discrimination 4 channels without discrimination (in dash box) Input range：1-3000 p.e. SSH：25/50/100ns ARCHGARD_V1 ARCHGARD stands for : Analog Readout Chip for GAmma Ray Detector Yan Xiangbo

  16. ARCHGARD V1 Simulation results • Noise performance • Output linearity Nonlinearity<1% 1-300p.e. 10-3000p.e. Yan Xiangbo

  17. ARCHGARD_V1test Noise~1/3pe 2mV ALTERA Development and Education Board 1pe 600mV 300p.e.（RC=50ns） Yan Xiangbo

  18. Archgard_v1 test result RC=25ns RC=50ns 2-350pe （3%，5pe~10%） 2-350pe（ 3%，2pe~29%） 10-3750pe（ 19%,200pe~50%） 10-3750pe （18%,200pe~50%） Yan Xiangbo

  19. ARCHGARD_V2 Difference with V1: • 16 channels • Gain choice：auto/forced • Peak holding • Trig latency • discrimination：int/ex trig • calibration • 16 trig/ 1 analog outputs Yan Xiangbo

  20. LHAASO project • LHAASO (Large High Altitude Air Shower Observatory) • It consists of several detectors : • KM2A : 1km2array, scintillator detectors • GEDA: Ground Electron Detector Array • GMDA: Ground Muon Detector Array • WFCTA: Wide Field Cherenkov Telescope Array • WCDA: Water Cherenkov Detector Array • SCDA • …… • KM2A, WFCTA, WCDA are readout with PMTs Gisèle Martin-Chassard

  21. ARGO AS LHAASO electronics need (I) • Complex detectors readout design • PMT readout for KM2A, WFCTA and WCDA • Lot of channels • Very large dynamic range for charge measurement: S.P.E. ~ thousands of PEs • The requirement for low power dissipation, high reliability  use of ASICs Gisèle Martin-Chassard

  22. LHAASO electronics need (II) 2 Channels for one PMT to achieve the dynamic range (8 PMTs for each ASIC) • Large dynamic range (1-3000pe) • PARISROC: 2 channels for 1 PMT • ARCHGARD: 1 channel for 1 PMT • flexibility for conversion rate • PARISROC: • Max. conversion time: 26us • Max. readout time:25us • One channel rate 5KHz • ARCHGARD: • Analog front-end • External ADC Gisèle Martin-Chassard

  23. CONCLUSION • PMm2 test setup at IPNO can be used to test modified PARISROC’s inputs both with generator and PMTs • The first tests will take place at Orsay in May 2012 with our chinese collegues • The system could be duplicated so that tests can be performed in China Gisèle Martin-Chassard

  24. Backup slides Gisèle Martin-Chassard

  25. Can we use one ASIC to deal with all detectors signal ? PARISROC2, ARCHGARD2 or a new one ? LHAASO detectors characteristics Gisèle Martin-Chassard

  26. KM2A (ED: electron detector; MD: muon detector) • PMT signal polarity : negative • Single channel hit rate: 1kHz (for ED); 10kHz (for MD) • Charge dynamic range: 1-3000 electron (for ED); 1-3000 muon (for MD) • Resolution: <25%@1e, <5%@3000e (for ED); <25%@1muon, <5%@3000muon (for MD) • Disc threshold: 0.25e (for ED); 0.25muon (for MD) • Time range: 0-10µs • Timing resolution (RMS): <1ns (for ED), <10ns (for MD) • Multi-hit resolution: 30ns • Total channels: 5137(for ED); 1209(for MD) Gisèle Martin-Chassard

  27. WCDA • PMT signal polarity : positive but could be negative • Single channel hit rate: 50kHz • Charge dynamic range: 1pe-4000pe • Shaping width: <350ns down to 1% • Peak error: <10% • Disc threshold: 0.25pe • Time range: 0-2000ns • Time bin: 1ns • Timing Precision (RMS): <0.5n • Multi-hit resolution: 25ns • Total channels: 900(channels)*4(stations) Gisèle Martin-Chassard

  28. WFCDA • PMT signal polarity : negative • Single channel hit rate: <5kHz • Charge dynamic range: 1pe-3000pe • Resolution: <50%@1pe, <1%@3000pe • Disc threshold can be adjusted: 0.25pe -- 100pe • Time range: 0-20us • Timing resolution (RMS): <100ns • Multi-hit separation: Yes • Multi-hit resolution: 1000ns • Total channels: 1024(channels)*24(stations) Gisèle Martin-Chassard

  29. Submarine test board ETHERNET with surface link • Analog front-end ASIC PARISROC • Altera Cyclone3 FPGA for slow-control and readout of the ASIC and data transmission from/towards the surface controller (mean 5 Mbps) • Single tunable (up to 2 kV) High Voltage via a 12-bit DAC • USB interface for standalone debugging PMT INPUTS PARISROC mezzanine TEST INPUT USB for tests Gisèle Martin-Chassard

  30. Charge measurement • Charge measurements • Two gain channels to cover the input dynamic range • Shaper with variable shaping time (25, 50 or 100ns) and gain • 8,9 or10-bit ADC • Charge resolution: max 0.2 p.e. (32 fC) for 10-bit ADC Input stage 2 input preamplifiers with adjustable gains (on 8 bits) Gain could vary by a factor 4 to compensate the PMTs gain spread Gisèle Martin-Chassard

  31. Time measurement Time measurements 2 systems: 1. Coarse time by 24-bit gray counter (Digital part) - working at 10 MHz - with 1.67 s of dynamic - 100 ns steps 2. Fine time by analog TAC - 100 ns dynamic - 220 ps step Gisèle Martin-Chassard

  32. Trigger efficiency S-Curve test Good linearity < 1% down to 35 fC= 5 σ noise σ= 7 fC threshold can be set at 1/3 of p.e. Gisèle Martin-Chassard

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