Implementing Low-Power CRC-Half for RFID Circuits

1. Implementing Low-Power CRC-Half for RFID Circuits Qi Mi & Zhi Li ECE 632 – Fall, 2008 University of Virginia

2. Outline • Introduction • Problem Statement • Contribution • Design • Simulation • Conclusion • Future Work • Q & A

3. Introduction • RFID applications • RFID security issues

4. Problem Statement • Constraint: • Energy – foremost constraint • Size • Complexity • Problem: We seek to find a feasible way of implementing low-power data encryption on RFID tags.

5. Contribution • Implemented the core hash function (i.e., CRC-Half) of CRC-MAC with PTM 90nm technology. • Analyzed energy at different operating voltages. • Gave an optimal operating voltage point for CRC-MAC. • Analyzed the trend of leakage current of the circuit.

6. CRC-MAC Briefing Fig 1. A hardware implementation of CRC-MAC

7. CRC-MAC Briefing (cont’d) Fig 2. C implementation of CRC-MAC as keyed one-way function

8. Circuit Design Fig 3. A symbol view of CRC-Half

12. Simulation

13. Optimization Design • Metric: Total energy consumption E/op = Eactive + Eleakage = CeffVDD2+ IlkgVDDTD • Knobs • Lower VDD (subthreshold design) Robust, require CMOS • Shorten operation duration

14. Simulation • Technology: PTM 90nm Technology • Circuit Description: netlists • Simulation Environment • Schematic-level • Software: FPGA Advantage 7.0 LS • Circuit-level • Software: Cadence 2005 • Simulator: Ocean with Spectre

15. Simulation (cont’d) • Approach

16. Spectre Simulation Result 1 0 1 1 Data word: 0010 1001 0010 1101 Key word: 1101 0010 0001 0111 Output: 1011 0001 0001 0111

17. Leakage Current Simulation Exponential Reduction as VDD decreases due to DIBL effect Leakage Current is independent of CLK rate

18. Current Waveform in One Cycle Pavg = α0→1fCeffVDD2 A higher CLK rate helps reduce energy consumption for a certain VDD

19. Total Energy per CRC cycle

20. Energy Consumption Plot • The optimal supply voltage is around 0.3V • Leakage energy consumption starts to dominate in the sub-threshold region • Leakage current is taking up a large proportion of average current

21. Conclusion • CRC-processing circuit is simulated in FPGA and Cadence • Average and leakage currents are simulated • Energy consumption comparison for different VDD and VDD optimization for minimum energy consumption

22. Future Work • Use multiple power supplies to speed up the critical path • Size up some parts of the circuit to increase speed • Add high VT NMOS to the PDN to reduce leakage

23. Q and A?

24. Thank you!