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CS 152 Computer Architecture and Engineering Lecture 11 Multicycle Controller Design Continued

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CS 152 Computer Architecture and Engineering Lecture 11 Multicycle Controller Design Continued

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    1. CS 152 Computer Architecture and Engineering Lecture 11 Multicycle Controller Design (Continued)

    2. The Big Picture: Where are We Now? The Five Classic Components of a Computer Today’s Topics: Microprogramed control Administrivia Microprogram it yourself Exceptions So where are in in the overall scheme of things. Well, we just finished designing the processor’s datapath. Now I am going to show you how to design the control for the datapath. +1 = 7 min. (X:47)So where are in in the overall scheme of things. Well, we just finished designing the processor’s datapath. Now I am going to show you how to design the control for the datapath. +1 = 7 min. (X:47)

    3. Controller Design The state digrams that arise define the controller for an instruction set processor are highly structured Use this structure to construct a simple “microsequencer” Control reduces to programming this very simple device ? microprogramming

    4. Multicycle Datapath

    5. State Diagram of Controller

    6. Using a Jump Counter

    7. Example: Jump-Counter

    8. Sequencer Sequencer-based control unit Called “microPC” or “µPC” vs. state register Control Value Effect 00 Next µaddress = 0 01 Next µaddress = dispatch ROM 10 Next µaddress = µaddress + 1 Dispatch ROM:

    9. Microprogramming (Maurice Wilkes) Control is the hard part of processor design ° Datapath is fairly regular and well-organized ° Memory is highly regular ° Control is irregular and global

    10. “Macro and micro - instruction” Interpretation

    11. Variations on Microprogramming ° “Horizontal” Microcode – control field for each control point in the machine ° “Vertical” Microcode – compact microinstruction format for each class of microoperation – local decode to generate all control points (remember ALU?) branch: µseq-op µadd execute: ALU-op A,B,R memory: mem-op S, D

    12. Extreme Horizontal

    13. More Vertical Format

    14. Hybrid Control

    15. Summary: Horizontal vs. Vertical Microprogramming

    16. Microprogramming a multicycle processor 1) Choose datapath and sequencer architecture 2) Assign states and sequence of each (multicycle) instruction (i.e. define the controller FSM) 2) Choose microinstruction format (minimum bits to describe all allowable functions of sequencer and datapath) 3) Map instructions into microinstruction sequences

    17. Sequencer Sequencer-based control unit Called “microPC” or “µPC” vs. state register Control Value Effect 00 Next µaddress = 0 01 Next µaddress = dispatch ROM 10 Next µaddress = µaddress + 1 Dispatch ROM:

    18. Datapath – single memory, single regfile Miminizes Hardware: 1 memory, 1 adder Putting it all together, here it is: the multiple cycle datapath we set out to built. +1 = 47 min. (Y:47)Putting it all together, here it is: the multiple cycle datapath we set out to built. +1 = 47 min. (Y:47)

    19. Finite State Machine (FSM) Spec

    20. Finite State Machine (FSM) Spec (improved)

    21. Designing a Microinstruction Set 1) Start with list of control signals 2) Group signals together that make sense (vs. random): called “fields” 3) Place fields in some logical order (e.g., ALU operation & ALU operands first and microinstruction sequencing last) 4) Create a symbolic legend for the microinstruction format, showing name of field values and how they set the control signals 5) To minimize the width, encode operations that will never be used at the same time

    22. 1) Start with list of control signals Signal name Effect when deasserted Effect when asserted ALUSelA 1st ALU operand = PC 1st ALU operand = Reg[rs] RegWr None Reg. is written MemtoReg Reg. write data input = ALU Reg. write data input = memory RegDst Reg. dest. no. = rt Reg. dest. no. = rd MemRd None Memory at address is read, MemWr None Memory at address is written IorD Memory address = PC Memory address = S IRWr None IR <= Memory PCWr None PC <= PCSource PCWrCond None IF ALUzero then PC <= PCSource PCSrc PCSource = ALU PCSource = ALUout ExtOp Zero Extended Sign Extended

    23. 2) Group into fields of unrelated signals Miminizes Hardware: 1 memory, 1 adder Putting it all together, here it is: the multiple cycle datapath we set out to built. +1 = 47 min. (Y:47)Putting it all together, here it is: the multiple cycle datapath we set out to built. +1 = 47 min. (Y:47)

    24. 2,3 & 4 ) Group into fields, order and assign names Field Name Values for Field Function of Field with Specific Value ALU Add ALU adds Subt. ALU subtracts Func ALU does function code Or ALU does logical OR SRC1 PC 1st ALU input <= PC rs 1st ALU input <= Reg[rs] SRC2 4 2nd ALU input <= 4 Extend 2nd ALU input <= sign ext. IR[15-0] Extend0 2nd ALU input <= zero ext. IR[15-0] Extshft 2nd ALU input <= sign ex., sl IR[15-0] rt 2nd ALU input <= Reg[rt] dest(ination) rd ALU Reg[rd] <= ALUout rt ALU Reg[rt] <= ALUout rt Mem Reg[rt] <= Mem Mem(ory) Read PC Read memory using PC Read ALU Read memory using ALUout for addr Write ALU Write memory using ALUout for addr Memreg IR IR <= Mem PCwrite PCwr PC <= PCSource PCSrc IF Zero then PCSource <= ALUout else ALU PCWrCond IF Zero then PC <= PCSource Seq(uencing) Seq Go to sequential µinstruction Fetch Go to the first microinstruction Dispatch Dispatch using ROM. Note: can specify combinations of fields that may not be possible or not work properly given the datapath (e.g., ALU operand and write register in single cycle)Note: can specify combinations of fields that may not be possible or not work properly given the datapath (e.g., ALU operand and write register in single cycle)

    25. 5) Encode each field Field Name Width Control Signals Set wide narrow ALU 4 2 ALUOp SRC1 2 1 ALUSelA SRC2 5 3 ALUSelB, ExtOp Dest 3 2 RegWrite, MemtoReg, RegDst Mem 3 2 MemRd, MemWre, IorD Memreg 1 1 IRWrite PCWrite 3 1 PCWr, PCSrc, PCWrCond Seq 3 2 AddrCtl Total width 24 14 bits

    26. 5) Encode each field (cont.) Code Name RegWrite MemToReg RegDest 00 --- 0 X X 01 rd ALU 1 0 1 10 rt ALU 1 0 0 11 rt MEM 1 1 0

    27. Finally – Do the microprogram…. Label ALU SRC1 SRC2 Dest. Memory MemReg. PCWrite Seq Fetch: Add PC 4 Read PC IR PCwr Seq Add PC Extshft Dispatch Rtype: Func rs rt Seq rd ALU Fetch Ori: Or rs Extend0 Seq rt ALU Fetch Lw: Add rs Extend Seq Read ALU Seq rt MEM Fetch Sw: Add rs Extend Seq Write ALU Fetch Beq: Subt. rs rt PCWrCond. Fetch

    28. Microprogramming Pros and Cons Ease of design Flexibility Easy to adapt to changes in organization, timing, technology Can make changes late in design cycle, or even in the field Can implement very powerful instruction sets (just more control memory) Generality Can implement multiple instruction sets on same machine. Can tailor instruction set to application. Compatibility Many organizations, same instruction set Costly to implement Slow

    29. Adding a more complex memory model

    30. Controller handles non-ideal memory

    31. Really Simple Time-State Control

    32. Time-state Control Path Local decode and control at each stage

    33. Overview of Control Control may be designed using one of several initial representations. The choice of sequence control, and how logic is represented, can then be determined independently; the control can then be implemented with one of several methods using a structured logic technique. Initial Representation Finite State Diagram Microprogram Sequencing Control Explicit Next State Microprogram counter Function + Dispatch ROMs Logic Representation Logic Equations Truth Tables Implementation PLA ROM Technique

    34. Summary Specialize state-diagrams easily captured by microsequencer simple increment & “branch” fields datapath control fields Most microprogramming-based controllers vary between: horizontal organization (1 control bit per control point) vertical organization (fields encoded in the control memory and must be decoded to control something) Steps: identify control signals, group them, develop “mini language”, then microprogram Control design reduces to Microprogramming Arbitrarily complicated instructions possible

    35. Summary: Microprogramming one inspiration for RISC If simple instruction could execute at very high clock rate… If you could even write compilers to produce microinstructions… If most programs use simple instructions and addressing modes… If microcode is kept in RAM instead of ROM so as to fix bugs … If same memory used for control memory could be used instead as cache for “macroinstructions”… Then why not skip instruction interpretation by a microprogram and simply compile directly into lowest language of machine?

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