1 / 17

CPU simulator Lab. Comp. & Sys. Eng. Dept. 2011/2012

First Term. 3 rd Year. CPU simulator Lab. Comp. & Sys. Eng. Dept. 2011/2012. CPU Simulator. Important: Give a tough simulate example to what is studied in computer organization course. Applications:

ulric-franklin
Download Presentation

CPU simulator Lab. Comp. & Sys. Eng. Dept. 2011/2012

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

  1. First Term 3rd Year CPU simulator Lab. Comp. & Sys. Eng. Dept. 2011/2012

  2. CPU Simulator Important: Give a tough simulate example to what is studied in computer organization course. Applications: Used in multinational companies that is cared to improve implementation of computer tasks and functions (Microsoft, IBM, Apple, Dell, …..etc).

  3. CPU Simulator Objectives : 1 - To create a new machine on CPU Sim with a given set of specifications in a correct way 2- To create an instruction set on a simulated machine on CPU Sim in a correct way 3- To write an assembly language program using a given instruction set on a given machine on CPU Sim in a correct way

  4. Related revision points - A program consist of some instructions , each instruction consist of some microinstructions which is the atomic operation of a CPU. - instruction is executed in two cycles : (Fetch cycle ) and ( execute cycle) Fetch cycle : fetch instruction from memory to instruction register . Execute cycle : execute the instruction in IR .

  5. Memory MAR PC Fetch cycle MBR IR Control unit

  6. Fetch Microinstructions T1 - MAR IR (Address field) T2 - MDR (Memory) T3 - IR (MDR) T4 - PC PC + 1 T5 - decode – ir

  7. Execute Cycle example LOAD microinstructions : MAR IR (Address field) MDR (Memory) ACC (MDR) LOAD Address field Mem MAR MBR ACC

  8. 1. Construct Hardware modules :

  9. 2. set registers and main memory

  10. 3. setting the microinstructions required

  11. 4. design the microinstruction that transfer data between registers 5. Design the microinstruction that transfer data between registers and memory

  12. 6. Design the microinstruction that increment the PC with 2 because memory isbyte addressable 7. Design the microinstruction that decode the IR registers

  13. 8. Design fetch sequence

  14. 9. Design jmpz instruction: jump if last Arithmetic operation is zero

  15. 10. Design the microinstructions of Jmpz

  16. Each student must read tutorial first before attend lab. Class. • Make sure your active email address is delivered to your TA where, your evolution and contact be easier. Questions

  17. Thank you Hisham Abdullah Teacher Assistant, C &S Eng. Dept., Zagazig Universty, Egypt

More Related