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PTA card Status

PTA card Status. Uplegger Lorenzo Testbeam 2002 meeting, Jan 17, 02 Fermilab. PTA Card. End of Memory. End of Memory. Soft Limit. Soft Limit. Addr pointer. Addr pointer. Memory Switch. MEZ. SW. Bank1. Bank0. End of Memory. End of Memory. Soft Limit. Soft Limit. Addr pointer.

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PTA card Status

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  1. PTA card Status Uplegger Lorenzo Testbeam 2002 meeting, Jan 17, 02 Fermilab

  2. PTA Card

  3. End of Memory End of Memory Soft Limit Soft Limit Addr pointer Addr pointer Memory Switch MEZ SW Bank1 Bank0

  4. End of Memory End of Memory Soft Limit Soft Limit Addr pointer Addr pointer Memory Switch MEZ SW Bank1 Bank0 DATA FLOW

  5. End of Memory Soft Limit Addr pointer Addr pointer Memory Switch End of Memory MEZ SW Soft Limit Bank1 Bank0 DATA FLOW

  6. End of Memory End of Memory Soft Limit Soft Limit Addr pointer Memory Switch MEZ SW Addr point = Soft Limit Bank1 Bank0 DATA FLOW

  7. End of Memory Soft Limit Addr pointer Memory Switch End of Memory SW MEZ Addr point = Soft Limit Interrupt Bank1 Bank0 DATA FLOW

  8. End of Memory Soft Limit Addr pointer Memory Switch End of Memory SW MEZ Addr point = Soft Limit Bank1 Bank0 DATA TO COMPUTER DATA FLOW

  9. End of Memory Soft Limit Addr pointer Memory Switch End of Memory SW MEZ Addr point = Soft Limit Bank1 Bank0 DATA TO COMPUTER DATA FLOW

  10. End of Memory Soft Limit Addr pointer Memory Switch End of Memory SW MEZ Addr point = Soft Limit Bank1 Bank0 DATA TO COMPUTER DATA FLOW

  11. End of Memory End of Memory Soft Limit Soft Limit Addr pointer Addr pointer Memory Switch SW MEZ Bank1 Bank0 DATA FLOW

  12. 31:0 31:0 31:0 31:8 7 6 5 4 3 2 1 0 31:4 3 2 1 0 31:0 Bank1 Address Pointer Bank0 Limit Bank1 Limit X B1LIMIT B1HFULL B1FULL B1EMPTY B1LIMIT B1HFULL B1FULL B1EMPTY X B1CNTCLR B1DIR B0CNTCLR B0DIR Bank0 Address Pointer OFF 0x08 OFF 0x0C OFF 0x10 OFF 0x14 OFF 0x18 OFF 0x1C BAR2 Configuration Registers

  13. 31:0 31:3 31:2 31:0 1 2 0 1 0 Read Clock Division Factor 31:2 X X BCO Clock Division Factor INTB1DATA 1 FAKEDATAEN 0 INTB0DATA CORETALK DATACNTCLR X TOGDIS SWTOG OFF 0x30 BAR2 Added Registers OFF 0x20 OFF 0x24 OFF 0x28 OFF 0x2C

  14. 31:3 31:0 31:0 2 1 0 31:2 Read Clock Division Factor BCO Clock Division Factor X FAKEDATAEN 1 0 CORETALK DATACNTCLR X TOGDIS SWTOG • No loss of data • Possibility to switch from software OFF 0x20 • Possibility to disable the switching mechanism OFF 0x24 OFF 0x30 OFF 0x28 FPGA Work done(1) • Switching is already implemented • Test mode • Simulate data taking. It allows to develop a software without connecting any chip • Read Out Clock • It is possible to use a readout clock up to 33Mhz • BCO Clock • It is possible to use a BCO clock up to 33Mhz

  15. 31:0 BAR5 OFF0x08 JN1SEL FPGA Work done(2) • Real Data: • We connected a preFPIX2I chip • We started using Gabriele software to read from the chip • We readout preFPIX2I chip data directly to PTA memory in parallel with Gabriele's software writing data to the screen. Successfully compared data on screen with data in PTA memory. • We generated our Readout clock and BCO clock and we filled the memories at high frequency. • Everything seems to work fine but we are planning to do some tests to measure the error rates.

  16. Software • Windriver is now installed on my Linux computer with Fermilab license • In collaboration with Stefano Magni (Milano) and Gianluca Alimonti (Milano) we started to develop C++ classes which represent our system • They installed the GPIB card on Linux. • Now they are also able to download Altera Firmware on Linux. • They are now working on this new system trying to figure out how to handle interrupts

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