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Logic style

AID–EMC: Low emission Digital Circuit Design. Logic style. Standard CMOS logic Pseudo NMOS logic MCML (MOS Current Mode Logic--differential version of CSL) CSL (CMOS Current Steering Logic). Why CSL ?. Target : Mixed-Mode Automotive Electronics Design

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Logic style

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  1. AID–EMC: Low emission Digital Circuit Design Logic style Standard CMOS logic Pseudo NMOS logic MCML (MOS Current Mode Logic--differential version of CSL) CSL (CMOS Current Steering Logic)

  2. Why CSL ? Target : Mixed-Mode Automotive Electronics Design Key aspect : di/dt + Power + Area + Speed Current Steering Logic

  3. CSL – Static Characteristic Vdd=2.5v I=20uA Design Parameter: R=

  4. CSL – Noise Margin Vdd=2.5v I=20uA

  5. CSL – Dynamic Characteristic Vdd=2.5v I=20uA

  6. The Effect of Decoupling Capacitance Cd Vdd=3.3v I=10uA R=6 1p 10p,100p,1n,10n There is a Trade off !

  7. Comparison of 16-bit RCA Note: Vdd=1.5v The curve of CSL 16-bit RCA was obtained by calculating the real speed F of the circuit, given the different supply current I. CMOS Power vs. Frequency (16-bit RCA) CSL 9.00E-04 8.00E-04 7.00E-04 • Solution: • power consumption management • power down strategies, • sleeping transistors, • … 6.00E-04 Power(Watt) 5.00E-04 4.00E-04 3.00E-04 2.00E-04 1.00E-04 0.00E+00 0 50 100 150 200 250 300 Frequency(Mhz)

  8. Spectrum Analysis of di/dt Power Spectral Analysis of the CMOS 16-bit RCA 150 140 30db decrease 130 120 110 Power 100 90 GABARIT ? 80 70 5 6 7 8 9 10 10 10 10 10 10 10 Frequency (Hz)

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