The output stage of the on pixel TDC demo chip

1. The output stage of the on pixel TDC demo chip Giulio Dellacasa GigaTracker Working Group CERN, September 2nd 2008

2. Overview Due to the high frequency clock (160 MHz), at least the output bus must be differential Giulio Dellacasa GTK Working Group

3. Data Format • Data are grouped in Frames • Definition of Frame: all the data which belong to the same turn of the Coarse Counter (6,4 μs) Giulio Dellacasa GTK Working Group

4. Column Controller Output Stage Integrated inside each column controller! Giulio Dellacasa GTK Working Group

5. Readout Options • Back pressure. When this signal is asserted (H) all the read operations are stopped (no data on the output bus, but still sent to the output FIFO). • Frame request: when asserted (H with a pulse width: 1÷16 clock cycles) ONLY ONE frame is transmitted to the output FIFO. If it is asserted for a longer time, ALL the frames are transmitted to the output FIFO, until the signal is released. If the signal is always down nothing is sent to the output FIFO. • Half rate: when asserted (H) the output bus (and its Dval flag) can be synchronized with an external 80 MHz clock. In order to slow down the output bus speed and to simplify the test/debug operations a set of options is provided: Giulio Dellacasa GTK Working Group

6. Half rate OFF Giulio Dellacasa GTK Working Group

7. Half rate ON Giulio Dellacasa GTK Working Group

8. Conclusions • Is it possible to have a common readout for both demonstrator chips? • A common readout interface is required in order to design a single acquisition system. The possibility of using (some of ) the readout blocks for both prototypes should be investigated • More detailed documents about these blocks can be found here: • http://personalpages.to.infn.it/~gdellaca/doc/na62/ Giulio Dellacasa GTK Working Group

9. MOSIS DM-LM options Only 2 layers for digital connections Giulio Dellacasa GTK Working Group