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Understanding Virtual Memory and Memory Hierarchy

This lecture provides an overview of virtual memory and its role in the memory hierarchy. It discusses the principles of locality, cache design choices, and the problems leading to the need for virtual memory. The lecture also explores segmentation and the concept of virtual-to-physical address translation.

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Understanding Virtual Memory and Memory Hierarchy

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  1. ELEC2041 Microprocessors and Interfacing Lectures 34: Virtual Memory - Ihttp://webct.edtec.unsw.edu.au/ June 2006 Saeid Nooshabadi saeid@unsw.edu.au Some of the slides are adopted from David Patterson (UCB)

  2. Overview • Virtual Memory • Page Table

  3. Cache Review (#1/2) • Caches are NOT mandatory: • Processor performs arithmetic • Memory stores instructions & data • Caches simply make things go faster • Each level of memory hierarchy is just a subset of next lower level • Caches speed up due to Temporal Locality: store data used recently • Block size > 1 word speeds up due to Spatial Locality: store words adjacent to the ones used recently

  4. Cache Review (#2/2) • Cache design choices: • size of cache: speed vs. capacity • direct-mapped vs. associative • for N-way set assoc: choice of N • block replacement policy • 2nd level cache? • Write through vs. write back? • Use performance model to pick between choices, depending on programs, technology, budget, ...

  5. { Thus far { Next: Virtual Memory Another View of the Memory Hierarchy Regs Upper Level Instr. Operands Faster Cache Blocks L2 Cache Blocks Memory Pages Disk Files Larger Tape Lower Level

  6. Virtual Memory • If Principle of Locality allows caches to offer (usually) speed of cache memory with size of DRAM memory,then why not, recursively, use at next level to give speed of DRAM memory, size of Disk memory? • Called “Virtual Memory” • Also allows OS to share memory, protect programs from each other • Today, more important for protection vs. just another level of memory hierarchy • Historically, it predates caches

  7. Code Static Heap Problems Leading to Virtual Memory (#1/2) ¥ • Programs address space is larger than the physical memory. • Need to swap code and data back and forth between memory and Hard disk using Virtual Memory) Stack >>64 MB Physical Memory 64 MB 0 0

  8. ¥ ¥ ¥ Stack Stack Stack Heap Static Code Static Heap Static Code Heap Code 0 0 0 Problems Leading to Virtual Memory (#2/2) • Many Processes (programs) active at the same time. (Single Processor - many Processes) • Processor appears to run multiple programs all at once by rapidly switching between active programs. • The rapid switching is managed by Memory Management Unit (MMU) by using Virtual Memory concept. • Each program sees the entire address space as its own. • How to avoid multiple programs overwriting each other.

  9. Segmentation Solution • Segmentation provides simple MMU • Program views its memory as set of segments. Code segment, Data Segment, Stack segment, etc. • Each program has its own set of private segments. • Each access to memory is via a segment selector and offset within the segment. • It allows a program to have its own private view of memory and to coexist transparently with other programs in the same memory space.

  10. Segmentation Memory Management Unit Virtual Address to memory segment selector logical address • Base: The base address of the segment • Logical address: an offset within a segment • Bound: Segment limit • SDT: Holds Access and other information about the segment Look up table held by OS in mem base bound Segment Descriptor Table (SDT) + >? physical address access fault

  11. Virtual to Physical Addr. Translation Program operates in its virtual address space • Each program operates in its own virtual address space; • Each is protected from the other • OS can decide where each goes in memory • Hardware (HW) provides virtual -> physical mapping Physical memory (incl. caches) HW mapping virtual address (inst. fetch load, store) physical address (inst. fetch load, store)

  12. Enough space for User D, but discontinuous (“fragmentation problem”) base+bound base Simple Example: Base and Bound Reg ¥ User C User B • Want discontinuous mapping • Process size >> mem • Addition not enough! User A OS 0

  13. Code Static Heap Mapping Virtual Memory to Physical Memory Virtual Memory ¥ • Divide into equal sizedchunks (about 4KB) Stack • Any chunk of Virtual Memory assigned to any chuck of Physical Memory (“page”) Physical Memory 64 MB 0 0

  14. Virtual Address Physical Address page 0 0 1K page 0 1K 0 page 1 1K 1024 1K page 1 Addr Trans MAP 1024 ... ... ... page 2 1K 2048 ... ... ... page 7 1K 7168 page 31 1K Physical Memory 31744 Virtual Memory Paging Organization (assume 1 KB pages) Page is unit of mapping Page also unit of transfer from disk to physical memory Addr Trans MAP is organised by OS

  15. Page Number Offset Virtual Memory Mapping Function • Cannot have simple function to predict arbitrary mapping • Use table lookup of mappings • Use table lookup (“Page Table”) for mappings: Page number is index • Virtual Memory Mapping Function • Physical Offset = Virtual Offset • Physical Page Number= PageTable[Virtual Page Number] (P.P.N. also called “Page Frame”)

  16. Virtual Address: page no. offset Page Table ... Page Table Base Reg V A.R. P. P. A. + index into page table Access Rights Physical Page Number Val -id Physical Memory Address . ... Address Mapping:Page Table (actually, concatenation) Reg #2 in CP #15 in ARM Page Table located in physical memory

  17. Page Table • A page table is an operating system structure which contains the mapping of virtual addresses to physical locations • There are several different ways, all up to the operating system, to keep this data around • Each process running in the operating system has its own page table • “State” of process is PC, all registers, plus page table • OS changes page tables by changing contents of Page Table Base Register

  18. Reading Material • Steve Furber: ARM System On-Chip; 2nd Ed, Addison-Wesley, 2000, ISBN: 0-201-67519-6. Chapter 10.

  19. Smart Mobile Phones • The Nokia’s Series 60 Platform: • software product for smart phones that Nokia licenses to other mobile-handset manufacturers. • runs on top of the Symbian OS. • The Series 60 Platform includes mobile • browsing, • multimedia messaging and content downloading, • personal information management and telephony applications. • software platform includes a complete and modifiable user interface library. - Licensees: Panasonic Mobile Communications, Samsung, Sendo, and Siemens (60% of market) • ARM PrimeXsys tools supplies the suite of pre-validated hardware and software

  20. A Page Table B Page Table Paging/Virtual Memory for Multiple Pocesses User A: Virtual Memory User B: Virtual Memory ¥ Physical Memory ¥ Stack Stack 64 MB Heap Heap Static Static 0 Code Code 0 0

  21. ... V A.R. P. P.N. Page Table Access Rights Physical Page Number Val -id P.T.E. V A.R. P. P. N. ... Page Table Entry (PTE) Format • Contains either Physical Page Number or indication not in Main Memory • OS maps to disk if Not Valid (V = 0) • If valid, also check if have permission to use page: Access Rights (A.R.) may be Read Only, Read/Write, Executable

  22. Things to Remember • Apply Principle of Locality Recursively • Manage memory to disk? Treat as cache • Included protection as bonus, now critical • Use Page Table of mappings vs. tag/data in cache • Virtual Memory allows protected sharing of memory between processes with less swapping to disk, less fragmentation than always swap or base/bound • Virtual Memory allows protected sharing of memory between processes with less swapping to disk, less fragmentation than always swap or base/bound in Segmentation

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